Released on September 28th, 2021.
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers of test cases build up, the risk of bug escapes increases.
Fortunately – and contrary to historical fears -- an exhaustive formal analysis can easily be applied here!
In this webinar, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.
Note that this webinar will be relatively technical: the examples will include RTL code -- familiarity with Verilog or VHDL is assumed. Additionally: this event will be focused on the introductory-level, basics of this topic. A future webinar will go deeper into more elaborate formal-based Data Path and Floating Point verification flows.
What You Will Learn:
- The difference between simulation and formal scoreboarding
- How to quickly setup a formal-based scoreboard with System Verilog Assertions (SVA)
- The scope of the data integrity analysis possible with this technique
Who Should Attend:
- Design & Verification engineers who are just getting started with formal property checking