Released on March 10th, 2022.
As FPGA design complexity and size continue to grow, additional design and verification team resources are required to be dedicated to the task of finding design issues. Too often, design problems are not discovered until later stages of the program when the design budget and time to market demand has little room for cost-growth due to unforeseen design IP integration problems.
The redesign cost of finding and fixing bugs grows directly with your FPGA design and its IP blocks' complexity. This webinar will show ways for improving your design IP quality to accelerate IP reuse, while finding RTL design issues early in the FPGA project lifecycle when these issues can be fixed quickly at lower cost impact.
This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.
What You Will Learn:
- When to consider deploying a Linter within your FPGA development lifecycle
- How to satisfy your FPGA design checking needs on a continuous QA basis
- What FPGA design problems can the Linter catch
Who Should Attend:
- Design & Verification Engineers & Managers