Release date: May 17th, 2023.
Correct connectivity in chip design is paramount for ensuring functionality, performance, design robustness, time-to-market, and cost-effectiveness. Application of proper connectivity verification helps identify and rectify issues from early phases, resulting in reliable and robust designs that perform as intended and meet market demands efficiently. Questa OneSpin Solutions Connectivity application offers advanced formal verification capabilities from interconnect exploration to chip-level end-to-end formal checks by employing advanced algorithms.
In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification. Will describe all types of possible connectivity checks and how to generate detailed analysis reports and debug tips to help engineers identify and resolve connectivity issues associated to them.
What You Will Learn:
- Importance of proper connectivity verification
- Design exploration for detailed connectivity specification
- Types of connectivity checks and issues associated with them
- Define abstract specification for high-scale designs
- Means to debug connectivity issues; structural, waveform, schematic
Who Should Attend:
- RTL Design Engineers
- Design Integrators
- Design Verification Engineers
Which Product(s) are Covered: