The Universal Verification Methodology (UVM) is a powerful verification methodology that was architected to be able to verify a wide range of design sizes and design types. One meaning of the “Universal” in the UVM name is that the methodology is intended to be capable of verifying anything and everything in the universe — at least all things in the realm of integrated circuits. There is value to this universal capability, but it also means there will likely be many capabilities in UVM that are not necessary for any specific project. Indeed, the authors maintain that there are many things in UVM that are not necessary for most projects. Furthermore, UVM originates from a blend of other verification methodologies such as OVM and VMM. These roots mean there are parts of UVM that were inherited from other methodologies, but which are not really needed in a pure UVM testbench. This featured DVCon 2015 session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly and become productive with using UVM for the verification of most types and sizes of digital designs modeled in VHDL, Verilog or SystemVerilog. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.
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