Released on February 16th, 2022.
Didn’t get to go to DAC 58? Catch up on the best of DAC in this technical presentation, which was recorded at DAC, followed by a live Q&A session hosted by the presenters.
Development projects stumble into issues that can cause project schedules to go awry, costing time, resources, and real money to remediate. But many of these issues are avoidable, even without having a testbench available, leaving project leaders to look for reasons why they weren’t avoided to begin with. This webinar will introduce you to a verification flow for designers that can help prevent early project issues, which when used result in lower cost, repeatable project attainment – without the silly excuses.
Functional verification teams sit in the critical path of project development. Their success is defined by something they really don’t have control over – the quality of incoming RTL. When designs are created under schedule pressures (and when are they not?) mistakes get made. Projects rush to verification to begin engaging the critical path. RTL can be coded and checked in faster than a testbench is ready, and the lack of a testbench is often blamed as the cause of lesser-quality code. This is an untenable situation in development today. This session will identify ways to remove the lack of a testbench as the cause of lower quality RTL.
What You Will Learn:
- How non-optimal RTL quality affects your development
- Why providing the highest quality RTL improves overall team performance
- How to accomplish an improved RTL quality-focused flow
Who Should Attend:
- Design & Verification Engineers & Managers