Released on June 4th, 2020
Even well-written constrained-random testbenches cannot traverse every part of a design’s state space. The truth is that simulation-based verification is fundamentally incomplete for even small DUTs. Additionally, it can take many weeks before a simulation testbench is created, providing a window of opportunity for complex bugs to be written into the IP. Consequently, whether the given bug is due to an out-of-date or misunderstood spec, or is a fundamental design flaw, the longer it goes undetected, the more expensive it is to find, fix, and thoroughly validate the repair both fixes the bug and doesn’t create unwanted side-effects itself. In this webinar we will show how formal property checking enables high-value verification long before other methods are available, exhaustively discovering any design errors that can occur (and without needing specific stimulus!)
What You Will Learn:
- How formal analysis works, and how it provides exhaustive results valid for all inputs and all time
- How you can create an effective "formal testbench" with very basic, easy-to-write properties
- An introduction to popular formal verification methodologies: bug hunting, completely proving the correctness of critical DUT functions, and proving the absence of deadlock
