Released on June 4th, 2020
Many high-value verification tasks such as dynamic connectivity verification, register policy verification, or confirming the integrity of critical signal paths and registers – require weeks or months of testbench development and execution, and still do not uncover all the unexpected corner cases. In contrast, formal-based verification can exhaustively verify these challenges via applications – “apps” – that are automated to the point where they effectively eliminate the need to know about the inner workings of formal analysis, yet deliver the exhaustive results needed. Questa Formal provides a powerful set of automated apps that can be applied from early in the design phase throughout the verification process to identify hard-to-find corner cases early in the verification process where they are easier and cheaper to fix. In this web seminar we will show how formal apps can help you address the following high-value verification challenges.
What You Will Learn:
- Finding deep bugs in complex logic and avoiding deadlocks (long before a UVM testbench is available!)
- Accelerating code coverage closure via dead code analysis
- Uncovering register policy corner cases
- Verifying the correctness of all SoC and pad ring direct, conditional, and sequential connectivity
- Finding unintended (or maliciously added) backdoors or “sneak paths” to secure/safety critical storage
- Root-cause analysis of erratic failures from ‘X’ propagation due to low power or post-reset bring-up, or X-optimism
- Validating low power clock gating logic, late ECOs or bug fixes, or fault/SEU mitigation logic
