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28 Results

• Better Stimulus Generation Through AI

  Paper - May 13, 2025 by Tom Fitzpatrick

  As semiconductor designs grow increasingly complex, verification teams face mounting pressure to ensure design correctness while meeting aggressive time-to-market demands. While PSS offers powerful capabilities for creating reusable verification assets, there are perceived adoption limitations. This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.

• Better Stimulus Generation Through AI

  Resource (Technical Paper) - May 13, 2025 by Tom Fitzpatrick

  This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.

• Accellera Sessions at DVCon U.S. 2025

  Resource (Verification Horizons Blog) - Jan 31, 2025 by Dennis Brophy

  As one of Accellera’s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and promote its important work on standards. For 2025 there will be five Accellera workshops, three on Monday and two on Thursday. I can’t recall a time when Accellera has had this many sessions covering its expansive work. Two of the workshop sessions come from Accellera initiated standards that are now IEEE standards.

• Celebrating the Approval of Portable Test and Stimulus Standard (PSS) 3.0

  Resource (Verification Horizons Blog) - Oct 09, 2024 by Dennis Brophy

  Accellera Systems Initiative  has recently announced the approval of the  Portable Test and Stimulus Standard (PSS) 3.0 , marking a significant milestone in verification of electronic systems. My colleague, Tom Fitzpatrick, wrote a nice blog a few weeks before the announcement highlighting his video presentation on how PSS and Verification IP fit together like a hand in a glove at DAC.

• Portable Stimulus and VIP: Like a Hand in a Glove

  Resource (Verification Horizons Blog) - Aug 08, 2024 by Tom Fitzpatrick

  Many of you know that I am particularly passionate about the Portable Stimulus Standard (PSS) and wanted to let you know that my recording of “Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove” is now available on Verification Academy .

• Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  In this session, you will learn that the Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviors that will execute, the test can easily be retargeted to different implementations for different environments.

• Exercising State Machines with Command Sequences

  Article - Dec 03, 2019 by Matthew Ballance

  Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design.

• Designing A Portable Stimulus Reuse Strategy

  Article - Dec 03, 2019 by Matthew Ballance

  The PSS language was designed with the requirements of test intent reuse, and automated test creation in mind. The requirement to allow test intent to be reused across a variety of very different platforms drove the PSS language to enable a clean and clear distinction between test intent and test realization, as shown in Figure 1. In a PSS description, test intent specifies the high-level view of what behavior is to be exercised.

• Results Checking Strategies with Portable Stimulus

  Resource (Technical Paper) - Aug 02, 2019 by Tom Fitzpatrick

  The key to results checking in Portable Stimulus is to understand that different levels of verification and validation environments have different needs when it comes to results checking. In a block-level environment, we might want detailed scoreboarding in addition to an overall per-operation pass/fail. In an SoC environment, we may only need an overall per-operation pass/fail.

• Portable Stimulus: Is It Revolution or Evolution?

  Conference - Jul 15, 2019 by Tom Fitzpatrick

  Many claim the new Portable Test and Stimulus Standard. (PSS) from Accellera will ignite the next revolution in SoC and Electronic System functional verification. Revolutionary innovation seeks to adapt the world to new and better ideas; yet it can be disruptive, expensive and produce unpredicted outcomes.

• Portable Stimulus: Is It Revolution or Evolution?

  Resource (Slides Download) - Jul 15, 2019 by Tom Fitzpatrick

  In this session, you will learn how Reuse can be the Evolution that enables the PSS Revolution.

• Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity

  Resource (Slides Download) - Jul 11, 2019 by Tom Fitzpatrick

  In this session, you will learn how you to use Portable Stimulus to leverage the built-in infrastructure in QVIP and your UVM environment to realize truly coverage-driven scenario-level functional coverage to keep you ahead of the productivity curve.

• Creating Tests the PSS Way in SystemVerilog

  Article - Jun 03, 2019 by Matthew Ballance

  Portable Stimulus is one of the latest hot topics in the verification space. Siemens EDA, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test and Stimulus Standard, a standard language that can be used to capture Portable Stimulus semantics.

• Auto-Generating Implementation-Level Sequences for PSS

  Article - Jun 03, 2019 by Amanjyot Kaur, Louie De Luna - Agnisys

  The Portable Test and Stimulus Standard (PSS) v1.0a aims to help the user describe the high-level test intent and create code for any downstream verification platform.

• Selecting a Portable Stimulus Application Focal Point

  Article - Feb 25, 2019 by Matthew Ballance

  As designs, especially System on Chip designs, have become more complex, the need for generated good, automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification.

• Choosing a Format for the Portable Stimulus Specification

  Resource (Technical Paper) - Feb 22, 2019 by Matthew Ballance

  This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms.

• Building a Better Virtual Sequence with Portable Stimulus

  Article - Nov 28, 2018 by Matthew Ballance

  When using the Universal Verification Methodology (UVM), sequences are the primary mechanism by which stimulus is generated in the testbench. Sequences come in two flavors: simple sequences for driving a single interface, and virtual sequences that control more complex behavior. Simple sequences tend to work with a single sequence item, while virtual sequences often spawn off multiple sub-sequences to accomplish their intended task.

• Portable Stimulus versus UVM: What's the Difference?

  Resource (Slides Download) - Jul 30, 2018 by John Aynsley

  We compare the Accellera Portable Test and Stimulus Standard (PSS) with the Universal Verification Methodology (UVM), and ask exactly what the difference is between the two when it comes to generating stimulus for hardware verification and SoC verification.

• Portable Stimulus: A New Hope

  Resource (Slides Download) - Jul 26, 2018 by Tom Fitzpatrick

  This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology.

• Portable Stimulus from IP to SoC - Achieve More Verification

  Resource (Slides Download) - Jul 26, 2018 by Matthew Ballance

  This session will explain the buzz about the emerging Accellera Portable Stimulus Standard and how users have long been applying Portable Stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity.

• Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

  Article - Jun 29, 2018 by Matthew Ballance

  Writing and reading registers is the primary way that the behavior of most IPs is controlled and queried. As a consequence of how fundamental registers are to the correct operation of designs, register tests are a seemingly-simple but important aspect of design verification and bring-up. At IP level, the correct implementation of registers must be verified – that they are accessible from the interfaces on the IP block and that they have the correct reset levels.

• Portable Stimulus is Here! (Almost)

  Resource (Slides Download) - Jul 20, 2017 by Tom Fitzpatrick

  The Portable Stimulus Standard promises to provide the next leap in verification productivity needed to support our ever-growing SoC verification challenges.

• Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow

  Article - Jun 28, 2017 by Mike Andrews, Mike Fingeroff - Siemens EDA

  Portable Stimulus has become quite the buzz-word in the verification community in the last year or two, but like most 'new' concepts it has evolved from some already established tools and methodologies. For example, having a common stimulus model between different levels of design abstraction has been possible for many years with graph-based stimulus automation tools like Questa inFact.

• Smoothing the Path to Software-Driven Verification with Portable Stimulus

  Article - Jun 28, 2017 by Matthew Ballance

  Designs are becoming more complex and increasingly include a processor – and often multiple processors. Because the processor is an integral part of the design, it's important to verify the interactions between software running on the processor and the rest of the design.

• Automating Tests with Portable Stimulus from IP to SoC Level

  Article - Feb 28, 2017 by Matthew Ballance

  Portable stimulus seeks to raise the level of abstraction and enable users to automate testing of the complex scenarios that emerge in subsystem- and SoC-level verification. However, the PSS under development by the Accellera PSWG builds on the base of constraint-based, transaction-level verification, which is already well-understood and widely deployed today.