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Low Power Apps: Shaping the Future of Low Power Verification
Resource (Technical Paper) - Feb 28, 2019 by
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Low Power Verification Forum
Webinar - Feb 05, 2019 by Gordon Allan
In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
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Industry Advancements Required to Close the Power Management Verification Gap
Webinar - Jan 28, 2019 by Sriram Hariharan
In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
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Deploying A Metrics Driven Low Power Methodology for Your RTL IP
Webinar - Jan 28, 2019 by Qazi Ahmed
In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
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Low Power Verification & Analysis with Emulation
Webinar - Jan 28, 2019 by Shantanu Samant
In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
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Productive Low Power Debug Across All Engines and Flows
Webinar - Jan 28, 2019 by Gordon Allan
In this session, we will answer the top nine questions asked for debugging low power in your design.
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A New Approach to Low-Power Verification: Power Aware Apps
Article - Dec 03, 2018 by Verification Horizons
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Power Aware Simplifies Parametric PA-SIM Regression
Resource (Slides) - Aug 02, 2018 by
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Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
Article - Jun 29, 2018 by Progyna Khondkar
PA-Static verification reporting of results are very straightforward and widely differ from PA-SIM in terms of format, contents, and representation. PA-Static reporting is mostly text based; however, visual representations of PA relevant logics and relevant UPF objects on schematic viewers often adds advantages for pin-pointing bugs and fixing them quickly.
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Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Webinar - Mar 07, 2018 by Ellie Burns
In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
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SATA Specification 3.3 Gaps Filled by SATA QVIP
Article - Mar 01, 2018 by Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA
Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.
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From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1
Article - Mar 01, 2018 by Progyna Khondkar
PA-Static verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).
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PA GLS: The Power Aware Gate-level Simulation
Article - Dec 06, 2017 by Progyna Khondkar
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Low-Power Design using High-Level Synthesis for Automotive Image Sensor
Resource (Slides) - Aug 07, 2017 by
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Artifacts of Custom Checkers in Questa® Power Aware Dynamic Simulation
Article - Feb 28, 2017 by Verification Horizons
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The Fundamental Power States for UPF Modeling and Power Aware Verification
Article - Jan 04, 2017 by Verification Methodology Team
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Is Your Power Aware Design Really X-Aware?
Article - Jan 03, 2017 by Verification Methodology Team
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Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
Article - Jan 03, 2017 by Verification Methodology Team
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Power Aware Libraries: Standardization and Requirements for Questa® Power Aware
Article - Nov 14, 2016 by Verification Horizons
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Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
Webinar - Sep 09, 2016 by Gordon Allan
In this session we will deliver five steps your team can take to improve first pass success, and how Questa enables your advanced verification goals every step of the way.
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Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
Paper - Aug 26, 2016 by Kurt Takara
In this paper, we begin by discussing the low power challenges for CDC design and verification including dynamic frequency and voltage scaling (DVFS). The following section describes the low power CDC verification methods and how these methods address the low power issues. Finally, we review some application examples for low power DVFS CDC verification.
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Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
Resource (Technical Paper) - Aug 26, 2016 by Kurt Takara
With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.
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Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Resource (Slides) - Apr 13, 2016 by Joe Hupcey
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Questa Visualizer - Power Aware Debug
Demo - Mar 18, 2016 by Chuck Seeley
In this demo, you will learn the UPF based Power Aware Debug features available in Visualizer with Questa PASim.
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Low Power Verification Techniques
Webinar - Sep 23, 2015 by Ellie Burns
This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach.