New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific


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    Authors: Amit Srivastava - Mentor GraphicsMadhur Bhargava - Mentor Graphics Abstract: The increasing complexity and growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. To keep up with the pace, the power formats have also evolved over the years. With the recent release of the IEEE P1801-2013 (UPF 2.1), several new features have been added along with improving clarity on existing features. It has also bridged the gap between UPF and CPF to provide much needed convergence. However, it has also posed some questions about the compatibility, differences, and challenges related to migration and its impact on verification. In this paper, we will provide an in-depth analysis and relevant examples of all the new features introduced by the UPF 2.1 along with highlighting any semantics differences with the earlier versions to help the user easily migrate to the new standard. Introduction: A. Power Management The growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. The constant need to minimize energy consumption to increase battery life for portable devices, and reduce heat dissipation for non-portable devices to minimize cooling costs ensure that power management is critical part of any electronics designs. Designers employ a variety of advanced techniques ranging from clock gating and power gating to multiple voltages and dynamic scaling of voltages and frequency. These techniques affect the functionality of the system if not executed correctly. Hence, it becomes important to verify the power management to ensure functional correctness of designs. The power management consideration starts as early as the system design phase to achieve maximum benefits. It gets refined at various phases of the design cycle. Thus it becomes important to verify the power management at every stage in the design flow so that any functional bugs are rectified. The traditional Hardware Description Languages (HDL) were not designed to consider the power related information in the description. Power intent specification formats were introduced to address this limitation. These formats allow the user to express the power intent related to power management, which can be overlaid on top of HDL description without requiring any change in normal design functionality. This specification can be used by various tools to perform verification and implementation of power managed designs. B. Verification Complexity Power management in today's complex SoCs involves various techniques. The result is the modification of the original design and insertion of special power management structures like isolation, level shifters, retention, etc. at various places in the design. Due to the complex interaction of these structures with the normal design functionality, it poses a serious challenge to verification. To add to it, the various IPs with their own power management need proper verification to remove any integration issues related to power management. To aid the verification process, power intent specification formats can share the burden by defining clear and consistent semantics enabling tools to automate various tasks related to power management. View & Download: Read the entire Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification technical paper. Download the presentation slides. Source: DVCon 2014