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1770 Results

Explore How to Protect Against Data Corruption with Formal Security Verification

Webinar - Feb 05, 2025 by Nicolae Tusinschi

In this session, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Webinar - Jan 22, 2025 by Nicolae Tusinschi

In this session, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process).In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
Boost Your Verification Productivity with Questa Verification IQ

Webinar - Nov 21, 2024 by Mark Carey

In this session, you will learn how to implement a collaborative, plan-driven verification process, complemented by a requirement-driven process for complete traceability from requirements to implementation and verification results.
Ensuring Robust Reset Integrity in Complex SoC Designs Through Advanced Reset Tree Checks

Resource (Verification Horizons Blog) - Nov 19, 2024 by Reetika - Siemens EDA

One of the foundational steps in the reset domain crossing (RDC) verification process is determining the structure of the reset tree within a system-on-chip (SoC) design. The reset tree is critical for tracking how reset signals propagate throughout the design, ensuring stable and predictable system operation. To construct this reset tree, engineers rely on static analysis techniques to examine the register transfer level (RTL) of the design and identify various reset signals.
Effective Identification of Reset Tree Bugs to Mitigate RDC Issues

Resource (Technical Paper) - Nov 15, 2024 by Reetika - Siemens EDA

This paper discusses these advanced structural checks, explaining how they are crucial for identifying potential issues early and ensuring the integrity of SoC designs.
Effective Identification of Reset Tree Bugs to Mitigate RDC Issues

Paper - Nov 15, 2024 by Reetika - Siemens EDA

This paper emphasizes the importance of advanced reset tree structural checks to identify potential design issues prior to conducting RDC analysis. By doing so, these checks can significantly conserve both the time and effort expended by designers throughout the overall RDC verification process. This paper advocates for early detection and correction of such issues, underlining how advanced reset tree checks can enhance the integrity and reliability of SoC designs.
Unlocking Performance: How Computational Storage Transforms Data Processing

Resource (Verification Horizons Blog) - Nov 07, 2024 by Ujjwal Negi, Prashant Dixit - Siemens EDA

Computational storage devices (CSD) represent a paradigm shift in how data processing and storage are handled in modern data centers, providing significant benefits for applications requiring large-scale data management and real-time analytics.
Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions

Resource (Slides) - Nov 06, 2024 by Rick Koster

This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.
Capturing Additional DFT Coverage thru Functional Fault Grading

Resource (Slides) - Nov 06, 2024 by Byron Brinson

Today’s Semiconductors often target a manufacturing test coverage in excess of 99%. This target is particularly important for chips used in safety critical applications. However, there are usually a small number of faults that cannot be covered by structural testing. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.
The New Leader in Verification IP: Questa + Avery Solution

Resource (Slides) - Nov 06, 2024 by Luis Rodriguez

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
Questa Verification IQ: Boost verification predictability and efficiency with Big Data

Resource (Slides) - Nov 06, 2024 by Ahmed ElKady - Siemens EDA

VIQ is a collaborative, browser-based, data-driven platform that revolutionizes the verification process. By harnessing the power of machine learning, VIQ delivers advanced analytics, enhanced collaboration capabilities, and comprehensive traceability. This innovative approach significantly boosts verification efficiency, empowering you to maximize your productivity.
Unlocking the Future of High Bandwidth Memory with Siemens and Rambus

Resource (Verification Horizons Blog) - Nov 05, 2024 by Dennis Brophy - Siemens EDA

HBM4 , the next-generation memory technology, is nearing finalization by JEDEC and promises to push the boundaries of data rate, 3D stack height, and DRAM chip density. This evolution from HBM3 to HBM4 means even higher bandwidth and greater device capacity, making it indispensable for the growing demands of AI and HPC applications.
Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Resource (Slides) - Oct 30, 2024 by Kamlesh Mulchandani

High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization.
Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Webinar - Oct 30, 2024 by Kamlesh Mulchandani

In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
Analyze Architecture for Next Level Formal Unreachability Analysis

Resource (Slides) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische
Analyze Architecture for Next Level Formal Unreachability Analysis

Resource (Recording) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische
Automated Coverage Exclusions with Increase Coverage

Resource (Slides) - Oct 17, 2024 by Damian Savage - Arm
Automated Coverage Exclusions with Increase Coverage

Resource (Recording) - Oct 17, 2024 by Damian Savage - Arm
Designing Secure and Performant Out-of-Order Processors Enabled by Formal Verification

Resource (Recording) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University
Designing Secure and Performant Out-of-Order Processors Enabled by Formal Verification

Resource (Slides) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University
Comprehensive Flow for Ensuring Integrity and Security Through Formal Verification

Resource (Slides) - Oct 17, 2024 by Keerthi Devraj
Comprehensive Flow for Ensuring Integrity and Security Through Formal Verification

Resource (Recording) - Oct 17, 2024 by Keerthi Devraj
Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

Resource (Slides) - Oct 17, 2024 by Dr. Jonathan Graf - Graf Research
Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

Resource (Recording) - Oct 17, 2024 by Dr. Jonathan Graf - Graf Research
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Resource (Recording) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische

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Webinar - Feb 05, 2025 by Nicolae Tusinschi

Webinar - Jan 22, 2025 by Nicolae Tusinschi

Webinar - Nov 21, 2024 by Mark Carey

Resource (Verification Horizons Blog) - Nov 19, 2024 by Reetika - Siemens EDA

Resource (Technical Paper) - Nov 15, 2024 by Reetika - Siemens EDA

Paper - Nov 15, 2024 by Reetika - Siemens EDA

Resource (Verification Horizons Blog) - Nov 07, 2024 by Ujjwal Negi, Prashant Dixit - Siemens EDA

Resource (Slides) - Nov 06, 2024 by Rick Koster

Resource (Slides) - Nov 06, 2024 by Byron Brinson

Resource (Slides) - Nov 06, 2024 by Luis Rodriguez

Resource (Slides) - Nov 06, 2024 by Ahmed ElKady - Siemens EDA

Resource (Verification Horizons Blog) - Nov 05, 2024 by Dennis Brophy - Siemens EDA

Resource (Slides) - Oct 30, 2024 by Kamlesh Mulchandani

Webinar - Oct 30, 2024 by Kamlesh Mulchandani

Resource (Slides) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische

Resource (Recording) - Oct 17, 2024 by Ahmed Soliman - Rheinland-Pfälzische

Resource (Slides) - Oct 17, 2024 by Damian Savage - Arm

Resource (Recording) - Oct 17, 2024 by Damian Savage - Arm

Resource (Recording) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University

Resource (Slides) - Oct 17, 2024 by Mohammad R. Faddideh - Stanford University

Resource (Slides) - Oct 17, 2024 by Keerthi Devraj

Resource (Recording) - Oct 17, 2024 by Keerthi Devraj

Resource (Slides) - Oct 17, 2024 by Dr. Jonathan Graf - Graf Research

Resource (Recording) - Oct 17, 2024 by Dr. Jonathan Graf - Graf Research

Resource (Recording) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische