Authors:
- Vidya Bellippady - Microsemi Corporation
- Sundar Haran - Microsemi Corporation
- Jay O'Donnell - Mentor Graphics
Abstract:
This paper describes a new verification technique using Test-IP, which are pre-built UVM test sequences implemented using a combination of directed, intelligent testbench (iTBA), and random methods. Test-IP converts an abstract test description defined in the UVM test into a series of protocol-specific burst sequence items passed to a standard verification-IP driver. This paper describes why the technique was first developed for AXI bus fabric applications and references a case-study where it was used to verify a 2-port AXI DDR controller.
The Test-IP approach differs from traditional approaches used with verification IP in the following ways:
- Eliminates user requirements to understand how the verification IP works when implementing tests. The user writes simple UVM tests
- Each UVM test populates a simple configuration (cfg) class specifying the type of bus traffic to be generated
- The cfg class contains user-defined address ranges/properties for peripheral addresses in the system. A set of cfgclass controls defining bus master agent capabilities are also provided
- Test-IP reads the cfg and generates traffic using intelligent testbench (iTBA) graph-based methods. iTBA graphs target stimulus combinations inferred by the cfg class which can be validated using traditional functional coverage metrics
- Supports optional generation of sequential address accesses for applications needing a more directed test approach
- Supports optional random selection of various protocol fields for use in constrained-random (CRT) applications
This technique vastly simplifies the test development process and achieves equivalent or superior functional coverage results in a fraction of the simulation time, and has applications in other verification work including bus fabric verification and performance profiling. Similar test-IP components have been implemented supporting the full set of AMBA protocols including AHB, AXI4, and ACE and used in related applications in both OVM and UVM environments.
Introduction:
Test-IP was first developed for an AMBA bus fabric application where the prior approach used a large number of directed sequences with limited functional coverage metrics. Test effectiveness was limited because it relied entirely on the user's capacity to write enough sequences without adequate feedback from functional coverage metrics. Test-IP supporting AXI was developed to address both the test capacity and test effectiveness problems.
Figure 1 shows a typical UVM fabric application using traditional directed sequences targeting AXI slaves in the system, with user-developed code highlighted in yellow. User directed sequences construct AXI bursts targeting various slaves required different addressing and burst construction depending on slave design. Unique sequences were needed for each master because different masters typically have different slave connectivity on the fabric. Each master would typically manage multiple outstanding read and write bursts which could interleave, further complicating the design of the sequences. Developing functional coverage to measure that each master accessed its target slaves generating the legal subset of AXI protocol supported by those slaves was too difficult to implement, leaving no effective means to assure tests were effective.
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Read the entire Using Test-IP Based Verification Techniques in a UVM Environment technical paper.
Source:
DVCon 2014
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