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Introduction:
One of the classic debates in computer science is whether a language should have a strongly-or weakly-typed data system. A strongly-typed language does not allow operations on data that are of incompatible types. Having strong types, as in VHDL, helps define intent and avoid errors, but is much more verbose. A weakly-typed language, such as Verilog, is more compact, but more difficult to debug without additional linting tools. These differences are some of the factors that HDL users often cite as reasons to prefer one language over the other.
SystemVerilog introduces strong types on top of the existing weaker Verilog data type system that can provide an environment similar to VHDL. SystemVerilog also introduces many new types used by the software developer that are useful for verification. This paper introduces methodologies for taking advantage of SystemVerilog’s type system for both the designer and verification engineer.
One of the fundamental differences between the Verilog and VHDL languages is their data type system. In Verilog, data types are all pre-defined (built-in), and implicit type conversion rules are defined for almost all types. Verilog is classified as a weakly-typed language. VHDL data types, on the other hand, are either predefined or user-defined, and require explicit type conversions between most un-equivalent types. VHDL is a strongly-typed language.1 This extra level of type definitions also gives VHDL the ability to express much higher level data types than Verilog.
As with most Hardware Description Languages, Verilog and VHDL have data types that have the ability to represent the binary structures that make up a digital design. These data types are the bit- and vector-level logical types and have served the design community for many years.
Both HDLs were created at a time when very few hardware engineers had a software background, although VHDL did address the need to design at higher levels of abstraction. However, the task of verification has become more of a software-oriented problem and neither language anticipated the additional that would place on them2.
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Read the entire Using Strong Types in SystemVerilog Design and Verification Environments technical paper.
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