- Mike Baird - WHDL
- Bob Oden - Mentor Graphics
With larger and more complex designs the gap between design and verification has grown larger. Because of this the reuse of the testbench both in new projects and within the same project has become very desirable. One of the "promises" of UVM is achieving such reuse. However, in reality, UVM reuse has been limited. This paper identifies the issues that affect UVM reuse and strategies for achieving reuse. A UVM reuse methodology will be presented that provides reuse of components from one testbench to another and within the same testbench from block to chip level.
With larger and more complex designs the gap between design and verification has grown larger. The verification effort relative to the design effort has grown until today most projects spend more time on verification than design. Because of this the reuse of portions of the testbench both in new projects and within the same project has become very desirable. One of the selling features or promises of UVM is achieving such reuse. However in reality, UVM reuse has been limited. While UVM provides testbench methodology, there is quite a bit of latitude as to how UVM testbenches are architected. There are many choices that the testbench architect has to make that effect reuse. Without forethought and planning for reuse, inevitably the architect makes some choices that limit reuse. These choices include how the components are structured and packaged, what the interfaces to the various blocks are for configuration etc. and how connection and configuration information is distributed. In this paper we look at some of the major issues that effect reuse and provide tested solutions to these issues.
Testbench Architecture and Component Packaging
In every UVM testbench there are parts that can possibly be reused and parts that cannot. One requirement then for reuse is to encapsulate and separate the reusable pieces from the non-reusable pieces. But simply lumping all the reusable parts together is not typically sufficient. Particularly when the DUT itself has multiple interfaces, buses, functional blocks etc.
The reusable parts of the testbench must be organized, grouped or packaged together to facilitate both block-to-top reuse with the same DUT and reuse with a different DUT. Additionally the architecture of the UVM testbench must provide an "interface" to the reusable piece so they can be integrated into another testbench or easily encapsulated within the existing testbench without modification. Other sections of this paper will discuss the "interface" requirements such as configuration, resource sharing and self-containment for these reusable pieces and in another section is discussed block-to-top reuse requirements. This section talks about the testbench architecture and packaging of the components.
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Read the entire Slaying the UVM Reuse Dragon technical paper.
DVCon US 2016