Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps | Technical Paper

Author:

Madhur Bhargava - Mentor, A Siemens Business

Introduction:

The effective verification of low-power designs has been a challenge for many years now. The IEEE 1801 standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs. One of the traditional yet effective way to verify the design is to write SV assertions to ensure that right design behavior is met. Verifying the low-power intent of the design using SV assertions is not straightforward because of the fact that there is disconnect between the traditional RTL and lowpower objects. Users can not access and manipulate the low-power object in the same way as they do for RTL. Lowpower concepts are abstract and the sources which form the low-power information are varied e.g. UPF, HDL and Liberty. Various tool vendors provide tool-generated low-power assertions to dynamically verify the design. Often these tool generated assertions do not suffice the user’s need and there is a requirements for additional checks. Users have also adopted varies ad-hoc approaches to write assertions in a checker module. One of these approach is to access the low-power objects using UPF commands and bind these checker modules into the design [2]. However as these checkers are written and compiled along with the design, they have to undergo the whole simulation process. Even a simple task of adding more assertions involves re-iteration of whole low-power simulation flow which is highly time inefficient specially when the simulations are run for larger SOCs.

Low-Power information model was introduced in UPF 3.0 which allows users to access and manipulate the lowpower objects. Once the handle of low-power objects is available, a lot of operations can be performed on them. In this paper we are going to demonstrate with the help of relevant examples and case studies that how we can leverage UPF 3.0 information model TCL query functions (aka Tcl Apps) and tool provided CLI commands to do low-power checking of the design. This is an innovative way of dynamically verifying the low-power intent after the simulation has completed and all the waveforms are available. The paper also explains how users can write their own checker TCL procedures for a specific scenario.

A. Power Intent Specification and Basic Concepts of UPF

IEEE Std 1801™-2015 Unified Power Format (UPF) allows designers to specify the power intent of the design. It is based on Tcl and provides concepts and commands which are necessary to describe the power management requirements for IPs or complete SoCs. A power intent specification in UPF is used throughout the design flow; however it may be refined at various steps in the design cycle. Some of the important concepts and terminology used in power intent specification are the following:

Power domain: A collection of HDL module instances and/or library cells that are treated as a group for power management purposes. The instances of a power domain typically, but do not always, share a primary supply set and typically are all in the same power state at a given time. This group of instances is referred to as the extent of a power domain
Power state: The state of a supply net, supply port, supply set, or power domain. It is an abstract representation of the voltage and current characteristics of a power supply, and also an abstract representation of the operating mode of the elements of a power domain or of a module instance (e.g., on, off, sleep)
Isolation Cell: An instance that passes logic values during normal mode operation and clamps its output to some specified logic value when a control signal is asserted. It is required when the driving logic supply is switched off while the receiving logic supply is still on
Level Shifter: An instance that translates signal values from an input voltage swing to a different output voltage swing
Hard macro: A block that has been completely implemented and can be used as it is in other blocks. This can be modeled by an hardware description language (HDL) module for verification or as a library cell for implementation
Retention: Enhanced functionality associated with selected sequential elements or a memory such that memory values can be preserved during the power-down state of the primary supplies

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