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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

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    Authors: Progyna Khondkar - Mentor GraphicsMadhur Bhargava - Mentor Graphics Introduction: The IEEE 1801-2015 specifies the new semantics for power states through the "add_power_state" UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concept actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states [1]. In practice we perceived these conceptual sets and extended them as foundation of for static and dynamic verification methodologies. Our approach shows validation procedures for UPF strategies. With design examples and case studies we also demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross coverage of power domains and supply sets, in more flexible and controllable ways. The realization of the power state concept allows us to probe further into the power management components for design and IP integration at different levels of design, from the RTL to PG-netlist. UPF is the power management methodology that facilitates adopting different power dissipation reduction techniques, like power gating and low-power standby etc. and allow to formalize the modeling and mapping of power specification on to a design. The fundamental constituent parts for UPF constructions are broadly based on the following categories. List 1. Fundamental Constituent Parts for UPF Constructions Design scopes for the UPFPower DomainsPower Domain Interfaces and Power Domain BoundariesPower Supply and Power Supply NetworksPrimary Power and Primary GroundPower States and Modes of Power OperationsPower Strategies View & Download: Login to view the The Fundamental Power States for UPF Modeling and Power Aware Verification technical paper.