- Hardik Parekh - ST Microelectronics
- Manish Kumar Karna - ST Microelectronics
- Mohit Jain - ST Microelectronics
- Atul Pandey - Mentor Graphics
- Sandeep Mittal - Mentor Graphics
Mixed signal system-on-chips (MSSoC) integrate digital and analog functions on the same chip. The increased analog content in today's SoCs is tightly integrated to the digital portion of the design. Market segments such as power management, automotive, communication, and security applications are driving ever more integration of analog and digital content on MSSoCs. SoC verification requires a lot of effort to achieve good functional coverage. Additional complexity in MSSoCs arises from the interconnection of signals flowing between digital and analog domains. To achieve good verification coverage on mixed signal SoCs, abstract models of analog components (henceforth called analog IP) are used. These abstract models, commonly called behavioral models, capture functional features of analog behavior in digital HDL languages and are orders of magnitude faster than simulating SPICE views of analog IP. To effectively use the behavioral models in SoC level verification, it is important to establish the equivalence between the model and the implementation (SPICE). This paper will present essential components of an equivalence validation environment and commonly used methods.
Mixed signal system-on-chips (MSSoC) integrate analog and digital functions on a single chip. As the complexity of MSSoCs increase, the task of functional verification becomes harder and harder. Verification of MSSoCs requires verifying the analog as well as the digital functional specification of the complete design in a single verification environment. Traditionally, this was done using mixed signal simulation. Mixed signal simulation integrates a SPICE (analog) solver with an event-based (digital) solver. The main benefit of mixed signal simulation is that the digital and analog IP in the design can be verified together, including their interconnections. Mixed signal simulation provides SPICE-level accuracy for the analog IP and is typically faster than pure SPICE simulation due to the use of a digital solver for the digital IP in the design. However, simulation performance of mixed signal simulators is still not as fast as a pure event driven (digital) simulator. Another limitation of Mixed Signal simulators is capacity. The current trend of integrating more functions on SoCs means more transistors in the design. The analog solvers in mixed signal simulators cannot handle large SPICE (analog) content.
Due to the above mentioned limitations, behavioral models of analog IP are used in the verification of SoCs. The analog behavioral models are event driven and analog behavior is captured using either real-number (RN) or logic data types in HDLs. Analog behavioral models are compatible with digital simulators and are orders of magnitude faster than a mixed-signal simulation . Functional verification of SoCs use behavioral models for analog design units to increase verification coverage on digital-analog interactions in the design. The use of behavioral models with digital simulation alleviates the capacity limitation of traditional mixed signal simulators. This approach enables the application of digital verification methodologies, such as verification planning and coverage tracking, to the analog IP in the design.
The behavioral model of analog IP is an abstract model of analog behavior. The more accurately the behavioral model represents analog behavior the slower its speed. Thus, to make it run faster, only relevant features for functional verification are implemented in the model; hence proving equivalence between the behavioral model and the actual implementation is a critical task.
This paper will describe our experience in setting up an equivalence validation environment for analog behavioral models with respect to the actual implementation (SPICE view). Section II presents a process oriented implementation of this environment. The need for verification planning, creating a test plan, monitoring progress, and coordinating team activity is discussed, as people with different skill sets are involved in this activity. The emphasis is on developing a methodology that can be easily extended and reused across different projects. Section III describes commonly used methods for equivalence validation. We refer to these methods as "equivalence validation components" (eqVC). The method chosen is based on the skill set of the verification team. The set up effort and various pros and cons of deploying each eqVC are also discussed. Section IV summarizes the results obtained and offers further recommendations.
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