- Dave Rich - Mentor Graphics
The hardware and software worlds have been drifting apart ever since John W. Tukey coined the terms "software" and "bit" back in 1958. Tukey introduced these terms as computers were evolving from electromechanical to electronic components. Hardware had long meant something you can touch and typically assemble from parts into a larger system. Software has come to mean that which you can't touch, yet that which you can change without touching the hardware. In the early age of software development, programmers required extensive knowledge of proprietary hardware architectures in order to write the programs that executed on them. Today, software programming has evolved to standardized languages, like C/++ and Java so programmers can write code independent of the hardware architecture the programs are running on. Finding engineers experienced in both disciplines is becoming very difficult making communication between software and hardware engineers daunting to say the least. This is further complicated because of different modeling languages used by each discipline and different abstraction levels required during each phase of a project.
Virtual Prototyping is an evolving methodology for the verification of software and hardware in a single environment that is designed to catch these communication breakdowns. Performance of this virtual prototype is critical to the successful completion of this verification task. Execution of software on simulated hardware models can be many orders of magnitude slower than the software executing on the real target hardware, so a virtual prototyping methodology partitions the execution of software and hardware into the proper abstraction level to achieve the desired performance versus accuracy trade-off.
This paper discusses various virtual prototyping methodologies available along with the verification and performance goals each is optimized to address. It will explain the trade-offs considering the different perspectives that hardware and software engineers are able to understand. In particular, this paper will demonstrate a virtual prototype using the modeling interface provided by the SystemVerilog "DPI-C" construct that bridges the C software world with Verilog Hardware Description Language (HDL) world.
Additionally, this paper will explain mechanisms for transaction-level communication between hardware and software using a UVM testbench. It will demonstrate software transactions on the C side that are converted into sequences of bus cycles represented by calls to the UVM register abstraction layer. This makes the hardware verification environment considerably reusable with the virtual platform environment.
By definition, a System-on-Chip (SoC) device is the blending of software and hardware domains. The architecture of an SoC is a compromise of trade-offs between implementation of tasks in hardware or software based on a number of performance goals. Verification of an SoC is usually divided independently into their respective domains before full system-level verification begins on the actual platform, or a representative prototype such as a hardware FPGA or emulation system implementation. Unfortunately, the availability of a full system usually comes too late in the project cycle to get the desired amount of verification completed in time. Virtual prototyping is a methodology that addresses this problem by getting earlier access to a full system using a variety of software emulation and simulation techniques.
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Read the entire Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI technical paper.