A New Approach to Low-Power Verification: Power Aware Apps

Introduction

One of the main challenges for low-power verification engineers has been the fact that there is a disconnect between the traditional RTL and low-power objects. Users cannot access and manipulate the low-power objects in the same way as they do the RTL objects. Low-power concepts are abstract and complexities arise because of the number of sources like UPF, HDL and Liberty all provide power intent in a low-power design. It has also been seen that the majority of verification time is spent debugging complex low-power issues.

There are not too many ways in which users can do self-checking of their designs. As the low-power architecture is complex and the number of power-domains used in designs is high, selective reporting of a part of a design is needed. The lack of an industry standard in this regard has resulted in inconsistencies in the different ad-hoc approaches adopted by different tool vendors.

To keep pace with the increasing complexity of low-power architectures, the IEEE 1801 standard is expanding its gamut of constructs and commands to include more low-power verification and implementation scenarios. In this article we will present some innovative ways of writing Power Aware Apps using the UPF 3.0 information model HDL package functions and Tcl query functions.

The paper also demonstrates how these Power Aware Apps can help in reporting, debugging and self-checking low-power designs. We will also highlight how these apps will help offer an efficient way to significantly save verification effort and time.

Power Intent Specification and Basic Concepts of UPF

The IEEE Std 1801-2015 UPF allows designers to specify the power intent of the design. It is based on Tcl and provides concepts and commands which are necessary to describe the power management requirements for IPs or complete SoCs. A power intent specification in UPF is used throughout the design flow; however it may be refined at various steps in the design cycle. Some of the important concepts and terminology used in power intent specification are the following:

• Power Domain: A collection of HDL module instances and/or library cells that are treated as a group for power management purposes. The instances of a power domain typically, but do not always, share a primary supply set and typically are all in the same power state at a given time. This group of instances is referred to as the extent of a power domain.
• Power State: The state of a supply net, supply port, supply set, or power domain. The power state is an abstract representation of the voltage and current characteristics of a power supply and the operating mode of the elements of a power domain or module instance (e.g., on, off, sleep).
• Isolation Cell: An instance that passes logic values during normal mode operation and clamps its output to some specified logic value when a control signal is asserted. It is required when the driving logic supply is switched off while the receiving logic supply is still on.
• Level Shifter: An instance that translates signal values from an input voltage swing to a different output voltage swing.
• Hard Macro: A block that has been completely implemented and can be used as-is in other blocks. This can be modeled by a hardware description language (HDL) module for verification or as a library cell for implementation.