Parameters used in a design in most cases must also be used in a testbench to ensure proper connections and communication can be performed. Parameterized UVM tests (which are not available by default) provide an easy mechanism for sharing of parameters.
Engineers create parameterized design IP so it can be verified once and then reused in multiple contexts. The parameters used in this IP can control design elements such as bus widths, generate statements to control if specific logic is available or not, etc. To verify the parameterized IP, the testbench must also have access to the parameters and knowledge of the values assigned to those parameters. With UVM being a hierarchical collection of objects with the test being the top level, why not just pass the same parameters to both the design and the UVM testbench. This will simplify the exploration of multiple parameter configurations and allow for verification of the full parameter state space.
This pattern is useful in cases where a design is parameterized and the full or at least multiple values of the parameter state space must be verified.
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