Intent:
The Dual Domain Hierarchy Pattern is an Environment Pattern to facilitate the design of testbenches that can be used for simulation as well as emulation, and across verification engines (or platforms) in general.
Motivation:
In order to enable and promote a verification process that is abstracted from underlying verification engines, particularly a software simulator and a hardware emulator, modern testbenches should be partitioned into two separated modeling domains, with different requirements, linked together to run in unison via transaction-level cross-domain data exchange. This is achieved by a dual domain testbench architecture with partitioned HVL and HDL module hierarchies, communicating through cross-domain function and task calls. The HDL domain is a synthesizable model to be compiled and run on the emulator (or other platform). It contains essentially everything that interacts directly with the RTL DUT or otherwise operates at the signal- level, namely the RTL DUT, clock and reset generators, and the various bus cycle state machines for driving and sampling DUT interface signals. The HVL domain is generally an untimed model with no explicit time advance references. It consists of non-synthesizable behavioral and object-oriented testbench code, including typically the various transaction-level stimulus and analysis components. Only transaction-based message passing can be performed between the two domains using "remote procedure invocations" in the form of function and task calls (i.e. cross-domain variable and signal references are not permitted).
Applicability:
The Dual Domain Hierarchy Pattern is applicable in any situation demanding a testbench with a common architecture for both simulation and emulation, and across verification engines in general.
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