This series of blog posts introduction Python as a verification language. cocotb an excellent way for Python to communicate to simulators. And pyuvm as a way to write UVM testbenches on top of cocotb.
Verification Horizons:
- Verification Learns a New Language
- Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
- Introduction to Coroutines
- Why a Python feature intended for I/O and asynchronous communication is perfect for verification.
- Cocotb Bus Functional Models
- How to use cocotb to write bus functional models in Python.
- Python and the UVM
- An introduction to pyuvm and how we can use it to write UVM code on top of cocotb.
- TLM 1.0 in pyuvm
- We’ll examine pyuvm’s implementation TLM 1.0 using simple producer/consumer examples. First we’ll handle blocking operations.
- The configuration database in pyuvm
- Now we turn our attention to some of the UVM’s utilities and how we use them in Python. The first of these is the UVM configuration database.
- The UVM Factory
- The pyuvm implements the UVM factory as it is described in the specification, removing elements that complicated the factory because of SystemVerilog typing.
- Logging in pyuvm
- This blog post provides a brief overview of logging and compares it to UVM reporting. Then it discusses logging in pyuvm.
- Odds and Ends
- This final blog post in the series discusses odds and ends that may have gotten little attention in the blog posts or may not have been invented when the blog post was written.
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