The following papers were presented at DVCon 2013.
by Matthew Ballance, Mentor Graphics Corporation
Today's complex designs increasingly include at least one, and often more, embedded processors. Given software's increasing role in the overall design functionality, it has become increasingly important to leverage the embedded processors in verifying hardware/software interactions during system-level verification. This paper presents a UVM-based package for software-driven verification, and presents applications of this package that enable more-comprehensive system-level verification.
by Ahmed Yehia, Mentor Graphics Corporation
In the paper, we give a quick overview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks, showing the simulation performance bottlenecks observed when performing on high-speed buses. We then present an efficient overlay layer that can be easily integrated on top of the UVM register library, making the library suitable for high as well as low performance systems. Then we show how an efficient, yet powerful, registers to AMBA AXI bus transactions adapter would look like in this case. Finally, we provide a cost-benefit analysis on current and proposed implementations.
by Dave Rich, Mentor Graphics Corporation
This paper discusses various virtual prototyping methodologies available along with the verification and performance goals each is optimized to address. It will explain the trade-offs considering the different perspectives that hardware and software engineers are able to understand. In particular, this paper will demonstrate a virtual prototype using the modeling interface provided by the SystemVerilog "DPI-C" construct that bridges the C software world with Verilog Hardware Description Language (HDL) world.
Additionally, this paper will explain mechanisms for transaction-level communication between hardware and software using a UVM testbench. It will demonstrate software transactions on the C side that are converted into sequences of bus cycles represented by calls to the UVM register abstraction layer. This makes the hardware verification environment considerably reusable with the virtual platform environment.
by Rich Edelman and Raghu Ardeishar, Mentor Graphics Corporation
The reader of this paper should be interested in predicting the behavior of his hardware or is interested in monitoring his hardware. This paper will review phase-level monitoring, transaction-level monitoring, and general monitoring. In-order and out-of-order transaction-level monitors and UVM constructs for single and multiple port monitors will be demonstrated, including discussion about simple function implementations versus FIFO and threaded implementations. A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. This monitor and scoreboard can model many AXI interactions, but under certain AXI usages, problems arise. For example partially written data may be read by an overlapping READ. This kind of behavior cannot be modeled by the "complete transaction" kind of monitor; it must be modeled by a phase-level monitor. Such a phase-level monitor will be demonstrated. All of these monitoring and scoreboard discussions can be widely applied to many protocols and many monitoring situations.
by Galen Blake, Altera Corporation and Steve Chappell, Mentor Graphics Corporation
As a design verification (DV) project is first started then steadily moves towards completion, the addition of verification features of increasing complexity in the testbench are a natural part of the development cycle. As these new features are added, a variety of controls are usually added to the testbench to manage the operations of these new and existing features. In many cases, this can lead to a chaotic set of text macro settings, compiler directives, configuration storage, parameters, plusargs, etc. to configure and control the topology and behavior of the testbench. Alternatively, multiple top-level testbench files (testbench netlists) or Perl script generated testbenches might be used to tame the complexity. Then for a final twist, modules and interfaces in the RTL context and class objects in the OVM/UVM context must all be configured to work together.
by NamDo Kim, JunHyuk Park, Byeong Min, Samsung Electronics Co., Ltd. and Wesley Park, Mentor Graphics
We propose a new register verification method that leverages formal verification to automatically generate a complete access policy specification for IP memory-mapped registers. While traditional register verification uses simulation to check IP compliance with a manually written specification, our method uses formal verification to automatically generate an IP compliant specification that designers manually check against their design intent. We introduce a register model that overcomes limitations in the expressiveness of the predefined UVM and IPXACT access polices. And, we present results from the successful application of our method to the register verification of three industrial designs.
by Rich Edelman and Raghu Ardeishar, Mentor Graphics Corporation
The reader of this paper is interested to use UVM sequences to achieve his test writing goals. Examples of UVM sequences will be used to demonstrate basic and advanced techniques for creating interesting, reusable sequences and tests.
by Mark Peryer, Mentor Graphics Corporation
Writing effective stimulus in UVM can prove to be challenging for various reasons, but not knowing about the relevant coding design patterns should not be one of them. There are various alternative techniques for writing sequences and choosing the right approach requires mastery of several styles. This paper describes seven common sequence design patterns which should prove useful to all UVM sequence writers. These patterns can be used stand-alone or combined to solve practical stimulus generation problems using UVM sequences.
by Shobana Sudhakar, Rohit K Jain, Mentor Graphics Corporation
Running a parallel simulation may be as easy as flipping on a switch with the progressive and maturing solutions available today, but do people really take full advantage of the technology? It is true that in some scenarios the overhead of communication and synchronization needed for parallel simulation can negate any substantial performance gains. However, there are scenarios where deploying the parallel simulation technology can provide tremendous benefit. A long running simulation that exercises large blocks of a design concurrently and independently is one good example.
Designers need to be aware of the factors that can inhibit the advantages of parallel simulations, even in these best-case scenarios; the main factor being inflexibility due to the way designs are modeled today. This paper focuses on these factors and is an effort to educate on best design principles and practices to maximize the advantage of simulation with parallel computing. The discussion also extends to the three main fundamental features of parallel simulations, viz., load balancing, concurrency and communication. Designers need to understand how their designs run in simulation with these factors to ensure they get the maximum out of parallel simulations.
by Bruce Mathewson, ARM Ltd. and Mark Peryer, Mentor Graphics Corporation
On-chip bus interconnect fabrics have become critical sub-systems in SoC platforms. Not only do they need to be functionally correct, but they also need to deliver the performance demanded by user applications in end products such as mobile platforms. The validation process for an interconnect in a simulation or emulation environment requires the generation of stimulus corresponding to a realistic use case. The typical brute force approach to this involves running applications software on processor cores that interact with the SoC RTL and checking that the overall design performance is satisfactory. An alternative approach is to validate the bus fabric stand-alone before integration with the rest of the SoC design using a verification environment that uses VIP to model the behavior of design IP. In order to create realistic traffic scenarios, the behavior of the different IP bus masters is described using traffic profiles. The performance of the interconnect is measured using instrumentation which monitors the bus activity. This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
by Adam Erickson, Mentor Graphics Corporation
This paper describes the purpose, requirements, development challenges, and applications of an open-source library for establishing standard TLM-based communication between SystemC (SC) and SystemVerilog (SV) models, including C/C++ models wrapped in SC or SV. It also describes a SystemC-side interface for controlling simulations based on the Universal Verification Methodology (UVM) in SystemVerilog. The UVM Connect library is available for download and has been proven to work on three major EDA vendors' simulators [1].
by Ahmed Yehia, Mentor Graphics Corporation
Given today's design sizes and complexities, complex verification environments are built to ensure high levels of quality, reliability, and stability are maintained in the DUV (Design Under Verification) before tape out. Yet, this challenges the ability to analyze and track the huge amount of data generated from today's verification environments and manage the underlying resources. Vast amounts of simulation and coverage data (due to huge regressions runs and long simulation cycles) need to be analyzed and tracked to help answer the important verification questions "Does it work?", "Am I done?", "What am I missing to get things done?", "How can I improve my productivity?"
The Accellera's Unified Coverage Interoperability Standard (UCIS) is a new, open, and industry-standard API just released in June 2012. It promises to facilitate and improve on verification productivity. It provides an application-programming interface (API) that enables sharing of coverage data across multiple tools from multiple vendors [1].
In this paper, we present several generic UCIS applications that can be easily developed and deployed to help improve the verification productivity, simulation throughput, coverage analysis, and coverage closure process..
by Michael Donnelly, Lockheed Martin, Doug Krening, Verification Consultant and Mike Horn, Mentor Graphics Corporation
In 2010–2011, Lockheed Martin Space Systems designed and verified eight FPGAs for the Command and Data Handling (C&DH) subsystem of the NOAA/NASA Geostationary Operational Environmental Satellite R-Series (GOES-R), scheduled to launch in 2015. Hardware validation and integration of these FPGAs went smoothly. Perhaps the best measure of the success: the FPGAs performed with almost no functional failures during integration and test. To help with this effort, Lockheed Martin created and introduced three new parts to its verification methodology. While originally developed in OVM, these techniques have subsequently been ported to UVM. UVM versions of the enhancements will be shown and discussed here. The three enhancements are:
1. Dramatically reducing agent development effort using a highly parameterized base agent
2. Providing data rate controls in a driver that preserves interesting transaction bursts and gaps while maintaining a desired throughput using an interface throttling class
3. Encapsulating, modifying and covering variations to an interface's pin-level timing using an interface timing class
