Browse all Papers in Siemens Verification Academy

March 2022

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  What Does the Sequence Say? Powering Productivity with Polymorphism

  UVM - Universal Verification Methodology Mar 23, 2022 Rich Edelman Paper

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  Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC

  UVMC Mar 23, 2022 Vishal Baskar Paper

April 2020

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  Deadlock Verification for Dummies: The Easy Way Using SVA and Formal

  Formal Verification Apr 15, 2020 Mark Eslinger Paper

August 2019

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  Transaction Recording: Anywhere Anytime

  UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman Paper

February 2019

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  UVM IEEE Shiny Object

  UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman Paper

February 2018

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  UVM and C Tests: Perfect Together

  UVM - Universal Verification Methodology Feb 26, 2018 Rich Edelman Paper

March 2017

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  Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

  Low Power Mar 20, 2017 Progyna Khondkar Paper

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  Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee

  Verification Management Mar 13, 2017 Thomas Ellis Paper

February 2017

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  DPI Redux. Functionality. Speed. Optimization.

  SystemVerilog Feb 28, 2017 Rich Edelman Paper

March 2016

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  No RTL Yet? No Problem: UVM Testing a SystemVerilog Fabric Model

  SystemVerilog Mar 15, 2016 Rich Edelman Paper

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  Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse

  UVM Framework Mar 01, 2016 Bob Oden Paper

February 2016

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  Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis

  Functional Safety Feb 28, 2016 Avidan Efody Paper

March 2015

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  Coverage Data Exchange is No Robbery…Or is It?

  Coverage Mar 03, 2015 Darron May Paper

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  Are You Smarter Than Your Testbench? With a Little Work You Can Be

  UVM - Universal Verification Methodology Mar 03, 2015 Rich Edelman Paper

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  UVM Sans UVM: An Approach to Automating UVM Testbench Writing

  UVM - Universal Verification Methodology Mar 02, 2015 Rich Edelman Paper

March 2014

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  Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?

  Verification Management Mar 06, 2014 Darron May Paper

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  Bringing Regression Systems into the 21st Century

  Verification Management Mar 03, 2014 Thomas Ellis Paper

February 2013

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  Boost Verification Results by Bridging the Hardware/Software Testbench Gap

  UVM - Universal Verification Methodology Feb 27, 2013 Matthew Ballance Paper

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  Register Verification: Do We Have Reliable Specification?

  Formal Verification Feb 27, 2013 Wesley Park - Siemens Eda Paper

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  Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

  UVM - Universal Verification Methodology Feb 27, 2013 Mike Horn Paper

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  Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

  UVMC Feb 27, 2013 Adam Erickson Paper

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  Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

  Verification IP Feb 26, 2013 Mark Peryer Paper

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  Sequence, Sequence on the Wall: Who's the Fairest of Them All?

  UVM - Universal Verification Methodology Feb 26, 2013 Rich Edelman Paper

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  Seven Separate Sequence Styles Speed Stimulus Scenarios

  UVM - Universal Verification Methodology Feb 26, 2013 Mark Peryer Paper

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  Boosting Simulation Performance of UVM Registers in High Performance Systems

  UVM - Universal Verification Methodology Feb 26, 2013 Ahmed Yehia - Siemens Eda Paper