Verification Academy

Topic	Replies	Views	Activity
Set_type_override_by_type OVM OVM	9	22383	April 7, 2017
Getting error as unexpected identifier and error in class specification UVM UVM	17	16652	May 13, 2016
P_sequencer, m_sequencer OVM OVM	12	19079	November 8, 2010
Mirroring in Register Abstraction Layer UVM UVM	16	16653	February 15, 2018
Best way to learn systemVerilog SystemVerilog SystemVerilog	13	18202	July 21, 2016
Config_db - parameters for set/get method UVM UVM , config_db	28	12288	February 19, 2020
Not able to find the package in the directory UVM UVM	14	16764	April 15, 2015
$display SystemVerilog SystemVerilog , display	14	16533	June 5, 2021
Force a DUT signal from a systemverilog class UVM UVM	14	15994	February 28, 2019
Creating multiple handles for covergroup in new constructor UVM UVM	19	13776	November 9, 2019
OVM World OVM OVM	27	11417	February 22, 2008
Syntax error : System verilog keyword 'void' is not expected to b used in this context OVM OVM	13	16019	September 11, 2012
Problem with Using do_pack and do_unpack OVM OVM	19	13381	November 16, 2009
How to set a queue/array in uvm_config_db? UVM UVM , uvm_config_db , queue	12	16444	July 29, 2020
How to work uvm using the modelsim tool UVM UVM	10	17760	September 12, 2015
Why the task body() inside sequence is of type virtual? OVM OVM	13	15601	May 19, 2019
UVM Phase Jumping UVM UVM	15	14483	July 4, 2016
APB READ_TRANSFER UVM UVM	32	9777	April 1, 2018
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	22	11688	May 29, 2025
How to update the mirror value of register UVM UVM , RAL , Mirrored-values-and-desired-values-in-UVM-RAL , mirrored-value , register-read-mirror-set_check_on_read	13	14963	February 9, 2018
A question about "-sverilog" option of vcs SystemVerilog SystemVerilog , sverilog-vcs-systemverilog	9	17454	November 6, 2014
"hot bit" randomization SystemVerilog SystemVerilog	11	15917	April 23, 2013
Need of super.build_phase(phase) UVM UVM , superbuild_phasephase	12	15134	March 19, 2022
Is there a way to use SVA property's local variable value to be used outside property SystemVerilog SystemVerilog	12	15014	June 17, 2021
When does the reg2bus and bus2reg are called in UVM register test? UVM UVM , reg2bus , bus2reg	9	16970	December 4, 2015
Disable fork join when one of the tasks complete SystemVerilog SystemVerilog , fork-join-in-loop , fork-join_any	12	14632	January 24, 2017
OVM World Site OVM OVM	24	10506	July 12, 2011
Enumeration error in systemverilog OVM OVM	9	16261	April 2, 2010
Correct way to kill sequences UVM UVM , stop_seqeunces	11	8183	August 2, 2024
Interface issue SystemVerilog SystemVerilog	11	14339	January 6, 2017
Overriding a parameter UVM UVM , parameter-override-class	9	15618	May 1, 2024
Connecting OVM Monitor with OVM Scoreboard! Wish would be helpfull for people! OVM OVM	16	11841	June 7, 2013
Is "assign_vi" the only way to pass interface to the components from environment? OVM OVM	18	11027	April 5, 2012
Start of simulation phase OVM OVM	10	14214	March 28, 2011
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	13559	September 23, 2014
Help about if statement in constraint block SystemVerilog SystemVerilog , constraint , if-statement-in-constraint , concatenation	17	11036	May 5, 2014
[problem] use interface array on Cadence tool OVM OVM	10	14081	June 15, 2010
What is the difference between ovm_transaction and ovm_sequence_item? OVM OVM	21	9741	September 19, 2014
Infinite Loop using While SystemVerilog SystemVerilog , Infinite-loop	13	12204	April 2, 2015
Doubt on "set_config_int" OVM OVM	10	13758	May 27, 2008
Implementing JK Flipflop in Verilog SystemVerilog SystemVerilog	10	13450	September 7, 2015
Printing topology in top module UVM UVM	14	11468	February 3, 2025
Difference between set_type_override and set_type_override_by_name OVM OVM	9	13979	June 14, 2010
Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer UVM UVM , killing_sequence , SEQREQZMB	14	11322	June 4, 2019
Coverage issue SystemVerilog SystemVerilog	10	13204	July 10, 2012
Watchdog Timer UVM UVM , watchdog	12	12108	November 3, 2014
Checking a clock using SVA SystemVerilog SystemVerilog , SVA , Duty-cycle	11	12368	August 18, 2016
Assertion to check for the pulses of the clock SystemVerilog SystemVerilog	12	11878	December 11, 2017
Communication between two agents in an env UVM UVM	16	10251	February 2, 2018
Ovm reporting OVM OVM	16	10224	July 23, 2013