Verification Academy

Topic	Replies	Views	Activity
Getting error as unexpected identifier and error in class specification UVM UVM	17	16600	May 13, 2016
P_sequencer, m_sequencer OVM OVM	12	19050	November 8, 2010
Mirroring in Register Abstraction Layer UVM UVM	16	16606	February 15, 2018
Best way to learn systemVerilog SystemVerilog SystemVerilog	13	17906	July 21, 2016
Config_db - parameters for set/get method UVM UVM , config_db	28	12182	February 19, 2020
Not able to find the package in the directory UVM UVM	14	16691	April 15, 2015
$display SystemVerilog SystemVerilog , display	14	16456	June 5, 2021
Force a DUT signal from a systemverilog class UVM UVM	14	15884	February 28, 2019
Creating multiple handles for covergroup in new constructor UVM UVM	19	13733	November 9, 2019
OVM World OVM OVM	27	11382	February 22, 2008
Syntax error : System verilog keyword 'void' is not expected to b used in this context OVM OVM	13	15993	September 11, 2012
Problem with Using do_pack and do_unpack OVM OVM	19	13365	November 16, 2009
How to set a queue/array in uvm_config_db? UVM UVM , uvm_config_db , queue	12	16337	July 29, 2020
How to work uvm using the modelsim tool UVM UVM	10	17668	September 12, 2015
Why the task body() inside sequence is of type virtual? OVM OVM	13	15548	May 19, 2019
UVM Phase Jumping UVM UVM	15	14321	July 4, 2016
APB READ_TRANSFER UVM UVM	32	9733	April 1, 2018
How to update the mirror value of register UVM UVM , RAL , Mirrored-values-and-desired-values-in-UVM-RAL , mirrored-value , register-read-mirror-set_check_on_read	13	14888	February 9, 2018
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	22	11566	May 29, 2025
"hot bit" randomization SystemVerilog SystemVerilog	11	15883	April 23, 2013
A question about "-sverilog" option of vcs SystemVerilog SystemVerilog , sverilog-vcs-systemverilog	9	17355	November 6, 2014
Need of super.build_phase(phase) UVM UVM , superbuild_phasephase	12	15032	March 19, 2022
Is there a way to use SVA property's local variable value to be used outside property SystemVerilog SystemVerilog	12	14920	June 17, 2021
When does the reg2bus and bus2reg are called in UVM register test? UVM UVM , reg2bus , bus2reg	9	16876	December 4, 2015
Disable fork join when one of the tasks complete SystemVerilog SystemVerilog , fork-join-in-loop , fork-join_any	12	14561	January 24, 2017
OVM World Site OVM OVM	24	10462	July 12, 2011
Enumeration error in systemverilog OVM OVM	9	16226	April 2, 2010
Interface issue SystemVerilog SystemVerilog	11	14295	January 6, 2017
How to use first_match in assertion SystemVerilog SystemVerilog , assertion , first_match	13	13180	July 31, 2022
Overriding a parameter UVM UVM , parameter-override-class	9	15529	May 1, 2024
Correct way to kill sequences UVM UVM , stop_seqeunces	11	7946	August 2, 2024
Connecting OVM Monitor with OVM Scoreboard! Wish would be helpfull for people! OVM OVM	16	11823	June 7, 2013
Is "assign_vi" the only way to pass interface to the components from environment? OVM OVM	18	10988	April 5, 2012
Start of simulation phase OVM OVM	10	14169	March 28, 2011
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	13497	September 23, 2014
[problem] use interface array on Cadence tool OVM OVM	10	14064	June 15, 2010
Help about if statement in constraint block SystemVerilog SystemVerilog , constraint , if-statement-in-constraint , concatenation	17	10975	May 5, 2014
What is the difference between ovm_transaction and ovm_sequence_item? OVM OVM	21	9724	September 19, 2014
Doubt on "set_config_int" OVM OVM	10	13739	May 27, 2008
Infinite Loop using While SystemVerilog SystemVerilog , Infinite-loop	13	12161	April 2, 2015
Implementing JK Flipflop in Verilog SystemVerilog SystemVerilog	10	13396	September 7, 2015
Difference between set_type_override and set_type_override_by_name OVM OVM	9	13925	June 14, 2010
Coverage issue SystemVerilog SystemVerilog	10	13165	July 10, 2012
Printing topology in top module UVM UVM	14	11223	February 3, 2025
Watchdog Timer UVM UVM , watchdog	12	11984	November 3, 2014
Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer UVM UVM , killing_sequence , SEQREQZMB	14	11139	June 4, 2019
Assertion to check for the pulses of the clock SystemVerilog SystemVerilog	12	11834	December 11, 2017
Checking a clock using SVA SystemVerilog SystemVerilog , SVA , Duty-cycle	11	12301	August 18, 2016
Ovm reporting OVM OVM	16	10190	July 23, 2013
Communication between two agents in an env UVM UVM	16	10188	February 2, 2018