Implementing JK Flipflop in Verilog

SystemVerilog
1

I’m trying to implement simple JK Flipflop in Verilog (Modelsim). But I’m getting the following error

The generate if condition must be a constant expression.
Here is the code which I’m using

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule

Can someone help me

2

I would use an always block to model a J-K ff.

  1. Define input: j,k,clk output:q, qbar
  2. Cover ALL the cases: when {j,k} equals 00, 01, 10, 11. This could be done with a case statement.
  3. Put all the logic in 2. inside a always block and sample on rising edge of the clk. Or falling if preferred.
  4. Most importantly, J-K ff is a Flip Flop, which means output value change on the clock edge. Comparing to a latch, the output value changes is based on clock level. With that being said, and examine your code again, you defined a clk but never use it. Or are you coping part of the code here?
3

In reply to tyyang:

Actually I’m trying to implement this Sequential Circuit

Here’s my code

seq_circuit1.v

module seq_circuit1(x, clk, Q0, Q1);
 input x, clk;
 output Q0, Q1;
 reg J0,K0,J1,K1;
always @(negedge clk)
begin
 //Blocking and Non Blocking both will work
 J0 = Q1 & ~x;
 K0 = Q1 & x;
 J1 = x;
 K1 = (Q0 & x) || (~Q0 & ~x);
 jkfflop JKff0 (J0,K0,Q0);
 jkfflop JKff1 (J1,K1,Q1);
end
endmodule

jkfflop.v

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule

I’m getting some errors and I’m unable to figure out why. Can you tell me where did I do it wrong

4

You have to use “If” statements in a procedural block(For you it should be in an “always” block) in jkfflop.v. You have to make the code clk sensitive in this file.

You can’t instantiate a module inside “always” block(In seq_circuit1.v).

Kiran

5

In reply to kiru2006:

Are you trying to say that, I’ve to code the whole thing in single file.

6

In reply to atinesh229:

No I am not saying that.
You can find examples on-line about how/where to write “if” statements and also how to instantiate a module.
Let me write a small template.

//How to write if statements
always @(posedge clk) begin
//if statement is present inside a always block
if(your condition) begin
your statements
end
end

//How to instatiate

module xyz;
//below instantiation is not inside always block
jkflop1(j1,…);
jkflop2(j2…);
//your codes
endmodule

Kiran

7

In reply to kiru2006:

I’ve modified the code like this

seq_circuit1.v

module seq_circuit1(x, clk, Q0, Q1);
 input x, clk;
 output Q0, Q1;
 reg J0,K0,J1,K1;
always @(negedge clk)
begin
 //Blocking and Non Blocking both will work
 J0 = Q1 & ~x;
 K0 = Q1 & x;
 J1 = x;
 K1 = (Q0 & x) || (~Q0 & ~x);
end
jkfflop JKff0 (J0,K0,Q0);
jkfflop JKff1 (J1,K1,Q1);
endmodule

and it compiled with no error. But still Code in jkfflop.v file has some errors.

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule

On Compilation I’m getting this error message
The generate if condition must be a constant expression.

Do you have any idea about this error.

8

In reply to atinesh229:

Please read “syntax” before coding.
Modified:

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;

always @(posedge clk) begin
if(J==0 & K==1)
begin
Q = 0;
end
else if(J==1 & K==0)
begin
Q = 1;
end
else if(J==1 & K==1)
begin
Q = ~Q;
end
end
endmodule

9

In reply to kiru2006:

Still same error.

10

In reply to atinesh229:

For me it is working.At least compiling if I change “output Q” to “output reg Q”
By the way it can’t be same error.
There are few more issues in your second file (sequence1.v).
I would suggest go through below link for good coding understanding.

http://www.asic-world.com/verilog/syntax.html

11

In reply to kiru2006:

Thanks kiru2006 all fixed. All file compiled with no error.
Sorry for asking stupid question, But I’m new to Verilog. Is the code correct implementation of the logic circuit(see image above).