Implementing JK Flipflop in Verilog

SystemVerilog
8

In reply to atinesh229:

Please read “syntax” before coding.
Modified:

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;

always @(posedge clk) begin
if(J==0 & K==1)
begin
Q = 0;
end
else if(J==1 & K==0)
begin
Q = 1;
end
else if(J==1 & K==1)
begin
Q = ~Q;
end
end
endmodule