Implementing JK Flipflop in Verilog

SystemVerilog
2

I would use an always block to model a J-K ff.

  1. Define input: j,k,clk output:q, qbar
  2. Cover ALL the cases: when {j,k} equals 00, 01, 10, 11. This could be done with a case statement.
  3. Put all the logic in 2. inside a always block and sample on rising edge of the clk. Or falling if preferred.
  4. Most importantly, J-K ff is a Flip Flop, which means output value change on the clock edge. Comparing to a latch, the output value changes is based on clock level. With that being said, and examine your code again, you defined a clk but never use it. Or are you coping part of the code here?