Implementing JK Flipflop in Verilog

In reply to atinesh229:

For me it is working.At least compiling if I change “output Q” to “output reg Q
By the way it can’t be same error.
There are few more issues in your second file (sequence1.v).
I would suggest go through below link for good coding understanding.

http://www.asic-world.com/verilog/syntax.html