Not able to find the package in the directory

susharma · April 15, 2015, 4:10am

Hello Team,

Please guide. How to import the package created in the project directory in the tb top file. I am importing in this way::

import spi_test_lib_pkg::*;

But it gives error

**** Error: C:\questasim_10.2c\examples\top_tb.sv(7): Could not find the package (spi_test_lib_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.**

Plus uvm_reg.svh and uvm_reg_map.svh are located at the following path:
C:\questasim_10.2c\verilog_src\uvm-1.1d\src\reg

These files are needed in the spi-apb environment.
I am trying to include these files but it gives more error. Please help me to clarify this.

I am learning SPI-APB verification using uvm-1.1d with Questasim-10.2c.

Thanks and Regards
Sunil Sharma

sushrutveerapur · April 15, 2015, 5:07am

Try this:

// Similar to package example shown below
`include "spi_test_lib_pkg_file_includes.sv"

module tb;

   // All package imports
   import uvm_pkg::*;
   import spi_test_lib_pkg::*;
...
...

Example (uvm_pkg.sv) of how a package looks:

`ifndef UVM_PKG_SV
`define UVM_PKG_SV

`include "uvm_macros.svh"

package uvm_pkg;

  `include "dpi/uvm_dpi.svh"
  `include "base/uvm_base.svh"
  `include "tlm1/uvm_tlm.svh"
  `include "comps/uvm_comps.svh"
  `include "seq/uvm_seq.svh"
  `include "tlm2/uvm_tlm2.svh"
  `include "reg/uvm_reg_model.svh"

endpackage

`endif

dave_59 · April 15, 2015, 5:11am

In reply to susharma:

How did you compile spi_test_lib_pkg? Packages must be compiled before they can be imported.

susharma · April 15, 2015, 6:13am

In reply to dave_59:

Hello Dave,

I am using Questasim-10.2c, I have all the files of SPI-APB from VA(in uvm) on the left panel including .v, .sv and .svh.
I just right click that panel and ->compile ->compile order → Auto generate-> ok.

I trying to import or include the file uvm_reg.svh and uvm_reg_map.svh in my environment.
But it gives error.

**Could not find the package (uvm_reg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
**
Please guide.

Regards
Sunil

susharma · April 15, 2015, 6:26am

In reply to Sushrut Veerapur:

Hello Sushrut,

I am doing as per your way:

`ifndef GUARD_SPI_REGISTER_PKG
`define GUARD_SPI_REGISTER_PKG

`include "uvm_macros.svh"
`include "spi_register_coverage.svh"
`include "C:/questasim_10.2c/verilog_src/uvm-1.1d/src/reg/uvm_reg.svh"


package spi_register_pkg;

import uvm_pkg::*;
import apb_agent_pkg::*;
import uvm_reg::*;
import uvm_reg_file::*;

But it gives error::

**** Error: spi_register_pkg.sv(9): near “package”: syntax error, unexpected package, expecting class**
Please guide.

Regards
Sunil

sushrutveerapur · April 15, 2015, 6:51am

In reply to susharma:

Can you please paste spi_register_pkg.sv file snippet here.

susharma · April 15, 2015, 7:20am

In reply to Sushrut Veerapur:

Hello Sushrut,

This is spi_register_pkg.sv file:

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

`ifndef GUARD_SPI_REGISTER_PKG
`define GUARD_SPI_REGISTER_PKG

`include "uvm_macros.svh"
`include "spi_register_coverage.svh"
`include "C:/questasim_10.2c/verilog_src/uvm-1.1d/src/reg/uvm_reg.svh"


package spi_register_pkg;

import uvm_pkg::*;
import apb_agent_pkg::*;
import uvm_reg::*;
import uvm_reg_file::*;


typedef struct packed {logic[31:0] bits;} word_t;

typedef struct packed {
bit[31:14] reserved; 
bit ASS; 
bit IE; 
bit LSB; 
bit TX_NEG; 
bit RX_NEG; 
bit GO_BSY; 
bit reserved_1; 
bit[6:0] CHAR_LEN;} ctrl_t;


typedef struct packed {
	                bit[31:16] reserved; 
		        bit [15:0] DIVIDER;} divider_t;

typedef struct packed { 
	                bit[31:8] reserved; 
		        bit[7:0] SS;} ss_t;

// This is for the SPIO TX/RX register which overlap
class spi_rw extends uvm_reg#(word_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_rw

// This is for the control register
class spi_ctrl extends uvm_reg #(ctrl_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_ctrl

// This is for the divider register
class spi_div extends uvm_reg #(divider_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0000_ffff;
  register_type = "RW";
  data = 32'h0000_ffff;
endfunction

endclass: spi_div

// This is for the slave select register
class spi_ss extends uvm_reg #(ss_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_ss

typedef uvm_register_base regs_array[];

class spi_register_file extends uvm_reg_file;

rand spi_rw spi_data_0_reg;
rand spi_rw spi_data_1_reg;
rand spi_rw spi_data_2_reg;
rand spi_rw spi_data_3_reg;
rand spi_ctrl spi_ctrl_reg;
rand spi_div spi_div_reg;
rand spi_ss spi_ss_reg;

  function new(string name = "spi_register_file",
               uvm_named_object register_container = null );

    super.new(name, register_container);

    spi_data_0_reg = new("spi_data_0", this);
    spi_data_1_reg = new("spi_data_1", this);
    spi_data_2_reg = new("spi_data_2", this);
    spi_data_3_reg = new("spi_data_3", this);
    spi_ctrl_reg = new("spi_ctrl", this);
    spi_ctrl_reg.WMASK = 32'b0000_0000_0000_0000_0011_1111_1111_1111;
    spi_ctrl_reg.UNPREDICTABLEMASK = 32'b0000_0000_0000_0000_0000_0001_0000_0000;
    spi_div_reg = new("spi_div", this);
    spi_div_reg.WMASK = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
    spi_ss_reg = new("spi_ss", this);
    spi_ss_reg.WMASK = 32'b0000_0000_0000_0000_0000_0000_1111_1111;
    this.add_register(spi_data_0_reg.get_fullname(), 32'h0000_0000, spi_data_0_reg, "spi_data_0");
    this.add_register(spi_data_1_reg.get_fullname(), 32'h0000_0004, spi_data_1_reg, "spi_data_1");
    this.add_register(spi_data_2_reg.get_fullname(), 32'h0000_0008, spi_data_2_reg, "spi_data_2");
    this.add_register(spi_data_3_reg.get_fullname(), 32'h0000_000c, spi_data_3_reg, "spi_data_3");
    this.add_register(spi_ctrl_reg.get_fullname(), 32'h0000_0010, spi_ctrl_reg, "spi_ctrl");
    this.add_register(spi_div_reg.get_fullname(), 32'h0000_0014, spi_div_reg, "spi_div");
    this.add_register(spi_ss_reg.get_fullname(), 32'h0000_0018, spi_ss_reg, "spi_ss");
   endfunction

   function bit check_valid_address(address_t address);
     bit result;

     result = addrSpace.exists(address);
     return result;
   endfunction: check_valid_address

   function regs_array get_regs();
     return '{spi_data_0_reg,
              spi_data_1_reg,
              spi_data_2_reg,
              spi_data_3_reg,
              spi_ctrl_reg,
              spi_div_reg,
              spi_ss_reg};
   endfunction: get_regs

endclass: spi_register_file

typedef uvm_reg_file reg_file_array[];

class spi_register_map extends uvm_reg_map;

  spi_register_file spi_reg_file;

  function new(string name, uvm_named_object parent);
    super.new(name, parent);
    spi_reg_file = new("spi_reg_file", this);
    this.add_register_file(spi_reg_file, 0);
  endfunction

  function reg_file_array get_register_files;
    return '{spi_reg_file};
  endfunction: get_register_files;

endclass

endpackage
`endif

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

sushrutveerapur · April 15, 2015, 9:51am

In reply to susharma:

Can you try changing this

`include "C:/questasim_10.2c/verilog_src/uvm-1.1d/src/reg/uvm_reg.svh"

to

`include "uvm_reg.svh"

add just add an +incdir to search for that file…

susharma · April 15, 2015, 12:56pm

In reply to Sushrut Veerapur:

Hello Sushrut,

Thanks for the workable effort. I have done one thing.

In uvm_pkg::*;, I have added the path of uvm_reg.svh, uvm_reg_map.svh file. Now it is working. With your approach, it is compiling uvm_reg.svh file completely and produce more errors.
I am not sure whether above hack is ok or not.
One more query, any reg file in uvm that accepts typedef struct packed as parameter, in the first class above , it is giving error in uvm_register(word_t) line.

Thanks and Regards
Sunil

cgales · April 15, 2015, 1:04pm

In reply to susharma:

You don’t ever want to include uvm_reg.svh or any other UVM source code file within your code. All of the UVM code is pre-compiled as part of the uvm_pkg. You will only ever need:

import uvm_pkg::*;
`include "uvm_macros.svh"

in all of your UVM based code. Note that there is no path specified in the uvm_macros.svh include directive. Importing uvm_pkg::* will provide access to all of the UVM classes, including the uvm_reg. There is no specific uvm_reg::* package.

If you include UVM source code directly in your package, you will cause multiple definitions and havoc will ensue.

susharma · April 15, 2015, 1:46pm

In reply to cgales:

Hello Cgales,

My environment is using the file like::->

My environment uvm available source file

uvm_register_map.svh uvm_reg_map.svh

And when I change the name, to uvm_reg_map, it gives error of,

Error in class extension specification.

I am trying to simulate SPI-APB uvm-1.1d environment in Questasim-10.2c.

Please help and guide.

Thanks and Regards
Sunil Sharma

cgales · April 15, 2015, 3:02pm

In reply to susharma:

Can you post your code and the exact error message that is given. It’s not clear what you are trying to accomplish. Are you trying to extend uvm_reg_map? How are you trying to do that?

susharma · April 15, 2015, 4:11pm

In reply to cgales:

Hello CGales,

The file : spi_register_pkg.svh and error is given below:

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
spi_register_pkg.svh
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

package spi_register_pkg;

import uvm_pkg::*;
`include "uvm_macros.svh"
`include "spi_register_coverage.svh"

import uvm_register_pkg::*;
import apb_agent_pkg::*;

typedef struct packed {logic[31:0] bits;} word_t;

typedef struct packed {
bit[31:14] reserved; 
bit ASS; 
bit IE; 
bit LSB; 
bit TX_NEG; 
bit RX_NEG; 
bit GO_BSY; 
bit reserved_1; 
bit[6:0] CHAR_LEN;} ctrl_t;


typedef struct packed {
	                bit[31:16] reserved; 
		        bit [15:0] DIVIDER;} divider_t;

typedef struct packed { 
	                bit[31:8] reserved; 
		        bit[7:0] SS;} ss_t;

// This is for the SPIO TX/RX register which overlap
class spi_rw extends uvm_register #(word_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_rw

// This is for the control register
class spi_ctrl extends uvm_register #(ctrl_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_ctrl

// This is for the divider register
class spi_div extends uvm_register #(divider_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0000_ffff;
  register_type = "RW";
  data = 32'h0000_ffff;
endfunction

endclass: spi_div

// This is for the slave select register
class spi_ss extends uvm_register #(ss_t);

function new(string l_name = "registerName",
             uvm_named_object p = null);
  super.new(l_name, p);
  resetValue = 32'h0;
  register_type = "RW";
  data = 32'h0;
endfunction

endclass: spi_ss

typedef uvm_register_base regs_array[];

class spi_register_file extends uvm_register_file;

rand spi_rw spi_data_0_reg;
rand spi_rw spi_data_1_reg;
rand spi_rw spi_data_2_reg;
rand spi_rw spi_data_3_reg;
rand spi_ctrl spi_ctrl_reg;
rand spi_div spi_div_reg;
rand spi_ss spi_ss_reg;

  function new(string name = "spi_register_file",
               uvm_named_object register_container = null );

    super.new(name, register_container);

    spi_data_0_reg = new("spi_data_0", this);
    spi_data_1_reg = new("spi_data_1", this);
    spi_data_2_reg = new("spi_data_2", this);
    spi_data_3_reg = new("spi_data_3", this);
    spi_ctrl_reg = new("spi_ctrl", this);
    spi_ctrl_reg.WMASK = 32'b0000_0000_0000_0000_0011_1111_1111_1111;
    spi_ctrl_reg.UNPREDICTABLEMASK = 32'b0000_0000_0000_0000_0000_0001_0000_0000;
    spi_div_reg = new("spi_div", this);
    spi_div_reg.WMASK = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
    spi_ss_reg = new("spi_ss", this);
    spi_ss_reg.WMASK = 32'b0000_0000_0000_0000_0000_0000_1111_1111;
    this.add_register(spi_data_0_reg.get_fullname(), 32'h0000_0000, spi_data_0_reg, "spi_data_0");
    this.add_register(spi_data_1_reg.get_fullname(), 32'h0000_0004, spi_data_1_reg, "spi_data_1");
    this.add_register(spi_data_2_reg.get_fullname(), 32'h0000_0008, spi_data_2_reg, "spi_data_2");
    this.add_register(spi_data_3_reg.get_fullname(), 32'h0000_000c, spi_data_3_reg, "spi_data_3");
    this.add_register(spi_ctrl_reg.get_fullname(), 32'h0000_0010, spi_ctrl_reg, "spi_ctrl");
    this.add_register(spi_div_reg.get_fullname(), 32'h0000_0014, spi_div_reg, "spi_div");
    this.add_register(spi_ss_reg.get_fullname(), 32'h0000_0018, spi_ss_reg, "spi_ss");
   endfunction

   function bit check_valid_address(address_t address);
     bit result;

     result = addrSpace.exists(address);
     return result;
   endfunction: check_valid_address

   function regs_array get_regs();
     return '{spi_data_0_reg,
              spi_data_1_reg,
              spi_data_2_reg,
              spi_data_3_reg,
              spi_ctrl_reg,
              spi_div_reg,
              spi_ss_reg};
   endfunction: get_regs

endclass: spi_register_file

typedef uvm_register_file reg_file_array[];

class spi_register_map extends uvm_register_map;

  spi_register_file spi_reg_file;

  function new(string name, uvm_named_object parent);
    super.new(name, parent);
    spi_reg_file = new("spi_reg_file", this);
    this.add_register_file(spi_reg_file, 0);
  endfunction

  function reg_file_array get_register_files;
    return '{spi_reg_file};
  endfunction: get_register_files;

endclass: spi_register_map



endpackage: spi_register_pkg

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

** Error: spi_register_pkg.sv(7): Could not find the package (uvm_register_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
** Error: spi_register_pkg.sv(33): near “uvm_register”: syntax error, unexpected IDENTIFIER
** Error: spi_register_pkg.sv(33): Error in class extension specification.

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////***********************************************************************************************************************************
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

Please guide.

Thanks and Regards
Sunil Sharma

cgales · April 15, 2015, 5:47pm

In reply to susharma:

There is no uvm_register_pkg. All of the UVM register functionality is contained within the uvm_pkg. That is why importing is is failing.

Is this an example from the Verification Academy. If it is, then we will need to look at updating it to the latest register implementation. There might be a few examples that use the old style that haven’t been updated.

Read the UVM Cookbook chapter on UVM Registers for the current implementation.

susharma · April 15, 2015, 7:00pm

In reply to cgales:

Hello Cgales,

Yes, it is example from VA. Thanks.

With Regards
Sunil Sharma.