In reply to Sushrut Veerapur:
Hello Sushrut,
This is spi_register_pkg.sv file:
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`ifndef GUARD_SPI_REGISTER_PKG
`define GUARD_SPI_REGISTER_PKG
`include "uvm_macros.svh"
`include "spi_register_coverage.svh"
`include "C:/questasim_10.2c/verilog_src/uvm-1.1d/src/reg/uvm_reg.svh"
package spi_register_pkg;
import uvm_pkg::*;
import apb_agent_pkg::*;
import uvm_reg::*;
import uvm_reg_file::*;
typedef struct packed {logic[31:0] bits;} word_t;
typedef struct packed {
bit[31:14] reserved;
bit ASS;
bit IE;
bit LSB;
bit TX_NEG;
bit RX_NEG;
bit GO_BSY;
bit reserved_1;
bit[6:0] CHAR_LEN;} ctrl_t;
typedef struct packed {
bit[31:16] reserved;
bit [15:0] DIVIDER;} divider_t;
typedef struct packed {
bit[31:8] reserved;
bit[7:0] SS;} ss_t;
// This is for the SPIO TX/RX register which overlap
class spi_rw extends uvm_reg#(word_t);
function new(string l_name = "registerName",
uvm_named_object p = null);
super.new(l_name, p);
resetValue = 32'h0;
register_type = "RW";
data = 32'h0;
endfunction
endclass: spi_rw
// This is for the control register
class spi_ctrl extends uvm_reg #(ctrl_t);
function new(string l_name = "registerName",
uvm_named_object p = null);
super.new(l_name, p);
resetValue = 32'h0;
register_type = "RW";
data = 32'h0;
endfunction
endclass: spi_ctrl
// This is for the divider register
class spi_div extends uvm_reg #(divider_t);
function new(string l_name = "registerName",
uvm_named_object p = null);
super.new(l_name, p);
resetValue = 32'h0000_ffff;
register_type = "RW";
data = 32'h0000_ffff;
endfunction
endclass: spi_div
// This is for the slave select register
class spi_ss extends uvm_reg #(ss_t);
function new(string l_name = "registerName",
uvm_named_object p = null);
super.new(l_name, p);
resetValue = 32'h0;
register_type = "RW";
data = 32'h0;
endfunction
endclass: spi_ss
typedef uvm_register_base regs_array[];
class spi_register_file extends uvm_reg_file;
rand spi_rw spi_data_0_reg;
rand spi_rw spi_data_1_reg;
rand spi_rw spi_data_2_reg;
rand spi_rw spi_data_3_reg;
rand spi_ctrl spi_ctrl_reg;
rand spi_div spi_div_reg;
rand spi_ss spi_ss_reg;
function new(string name = "spi_register_file",
uvm_named_object register_container = null );
super.new(name, register_container);
spi_data_0_reg = new("spi_data_0", this);
spi_data_1_reg = new("spi_data_1", this);
spi_data_2_reg = new("spi_data_2", this);
spi_data_3_reg = new("spi_data_3", this);
spi_ctrl_reg = new("spi_ctrl", this);
spi_ctrl_reg.WMASK = 32'b0000_0000_0000_0000_0011_1111_1111_1111;
spi_ctrl_reg.UNPREDICTABLEMASK = 32'b0000_0000_0000_0000_0000_0001_0000_0000;
spi_div_reg = new("spi_div", this);
spi_div_reg.WMASK = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
spi_ss_reg = new("spi_ss", this);
spi_ss_reg.WMASK = 32'b0000_0000_0000_0000_0000_0000_1111_1111;
this.add_register(spi_data_0_reg.get_fullname(), 32'h0000_0000, spi_data_0_reg, "spi_data_0");
this.add_register(spi_data_1_reg.get_fullname(), 32'h0000_0004, spi_data_1_reg, "spi_data_1");
this.add_register(spi_data_2_reg.get_fullname(), 32'h0000_0008, spi_data_2_reg, "spi_data_2");
this.add_register(spi_data_3_reg.get_fullname(), 32'h0000_000c, spi_data_3_reg, "spi_data_3");
this.add_register(spi_ctrl_reg.get_fullname(), 32'h0000_0010, spi_ctrl_reg, "spi_ctrl");
this.add_register(spi_div_reg.get_fullname(), 32'h0000_0014, spi_div_reg, "spi_div");
this.add_register(spi_ss_reg.get_fullname(), 32'h0000_0018, spi_ss_reg, "spi_ss");
endfunction
function bit check_valid_address(address_t address);
bit result;
result = addrSpace.exists(address);
return result;
endfunction: check_valid_address
function regs_array get_regs();
return '{spi_data_0_reg,
spi_data_1_reg,
spi_data_2_reg,
spi_data_3_reg,
spi_ctrl_reg,
spi_div_reg,
spi_ss_reg};
endfunction: get_regs
endclass: spi_register_file
typedef uvm_reg_file reg_file_array[];
class spi_register_map extends uvm_reg_map;
spi_register_file spi_reg_file;
function new(string name, uvm_named_object parent);
super.new(name, parent);
spi_reg_file = new("spi_reg_file", this);
this.add_register_file(spi_reg_file, 0);
endfunction
function reg_file_array get_register_files;
return '{spi_reg_file};
endfunction: get_register_files;
endclass
endpackage
`endif
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////