Start of simulation phase

OVM
1

Hi Friends,

I want to know real application of start of simulation phase.
If any configuration we can do through build than what is the exact application of start of simulation phase? can any one give real example of it?

Thanks in advance,

2

Akshay,

Many of the phases in the OVM are patterned after traditional simulation in pure Verilog/VHDL environments. The end_of_elaboration()/start_of_simulation() phases are mainly there as hooks for PLI/DPI applications or to communicate with any other environment with their own phasing.

In SystemVerilog, all static variable declarations initializations occur at time 0 before any initial/always processes begin. The start_of_simulation() phase is intended to represent the place you would perform variable initializations, and the run() phase represent the start of the initial processes.

In reality, the run_test() method is called in a process that could be after time 0. So start_of_elaboration() is your last oppertunitiy to initialize anything before starting the time consuming run() phase.

Dave Rich

3

Hi Dave,

good to see your quick response.

Can’t we do that initialization in build phase in OVM? as build phase executes at 0 time only.

PLI/DPI can be one application. But i don’t know much about that.
any other example of general verification where we can use this start of simulation phase and that we can’t do in build phase?

Thanks,

4

Hi Akshay,

From verification point of view, you can have your start banner of a test case or verification environment in start_of_simulation() function.

Further, you can print your topology and all the configurable parameters in start_of_simulation after the banner. This enables the user to see the configuration in which the test case is run.

I hope this makes things clear.

Thanks,
Ashish

5

Ashish

I think these things we can do from build phase as well. can’t we?

6

No Akshay.

You cannot. Its not advisable. You topology does not merely depending on newing the blocks. You need to connect the different components which is done in connect phase. ONly then you can say that topology is complete.

So build is not an ideal place to print the topology.

Ashish

7

what about printing topology in the phase connect in last?
also we can do that in end of elaboration phase isn’t it?
if we can do there than why we require start of simulation phase?

8

Akshay,

At the end of the connect phase, you will have information of that component only. And not for the entire topology. So printing cannot be done at the end of connect phase.

Yes, I agree for simple env we can also print the banner in end_of_elaboration. But that function is not intended for that.

Basically end_of_elaboration() validates the connections done in connect method. Further you are allowed to alter the connections or fine tune it in end_of_elaboration.

So start_of_simulation() is specifically given for banners et al.

Ashish

9

Thanks Ashish,

Now i got one application of start of simulation phase.
can you give me another example if you have?

10

In SystemVerilog, all static variable declarations initializations occur at time 0 before any initial/always processes begin. The start_of_simulation() phase is intended to represent the place you would perform variable initializations, and the run() phase represent the start of the initial processes.
Dave Rich

Dave,

I ran a short experiment and observed that start_of_simulation happens after initial block… Is there a dis-connect. I could not see any specific order of execution between initial block and start_of_simulation phase in uvm guide.

11

All of the OVM phases execute as part of the thread that calls run_test(), usually an initial bock. The only ordering that is guaranteed is within the OVM phases. If you want to guarantee ordering with other initial blocks, you would have to delay calling run_test.

BTW, there is a backward incompatible change in the UVM in that it does not allow you to call run_test() at a time other than time 0.

Dave