How to update the mirror value of register

I got stuck with the updating mirrored value of RO register in RAL.
I have a Read only register “status” in the RTL. and i have RAL integrated on to it.
The “status” register is Readonly register. We do not write any thing from TB side. But iam seeing from error that Mirror value of register is not getting updated.

Note: The register is Read only register.

UVM_ERROR reporter [RegModel] Field active_cells (datapathregs.STATUS[23:0]) mismatch read=24’h3ffc mirrored=24’h0.

I have two questions here:

  1. When the comparison of RTL and mirror value happens? because i do not see any compare() or mirror() method used in TB. But still this error comes as the comparison happens.Is there any other case that comparison happens other than mirror() and compare() methods?

I see only read operation from this register “status”.

How can i update the Mirrored value i.e RAL register value so that comparison RTL and mirror value will pass. I tried using predict() like predict(1) it worked. But here i want to pass the uvm_reg_type to predict. Because the value will be changed by DUT based on some internal operation.

  1. Do i need to call predict() method before read of the register or later?
    does setting set_auto_predict() and set_check_on_read() works in this case? I tried, but did not work.

Can some one help on this how to resolve issue?


In reply to murali405:

the mirror() method reads the Register in the RTL and is updating the value in the regmodel of the TB. IF you do not have a mirror command in your reg sequences you have to face compare errors.

In reply to chr_sue:

I tried using mirror() using front door access method in sequence before doing read() of the register and still i see that mirrored value of the read only register is “0”.
Can you reply to my questions in the thread? that will be helpful to figure out the issue.


In reply to murali405:
In your case I’d check the Integration of your Register model and the Connections, i.e. checking the Adapter and the predictor.

In reply to chr_sue:
But i observed that value updated using predict method is reflected on mirrored value, but same is not updated when i am using ucm_reg_type.

ex:1 map1.status1.predict(20) // It worked and reflects on mirroe value in comparison.
ex:2 uvm_reg_type rddata;
map1.status1.predict(rddata) // did not work. still getting 0 on mirrored value.
I can see that my register model and connections are correct.

In reply to murali405:

You mean uvm_reg_data_t? Correct?
This is a 2 state data types. It Looks like the mirror does not work and Returns the default value of a 2 state data type.
Could you please use uvm_reg_data_logic_t? If my guess is correct it should return ‘x’.

In reply to chr_sue:

May i know the use of “uvm_reg_data_logic_t”? How it will resolve my problem? I will get “x” instead of 0 but how can i get the updated mirrored value?

I observed one more thing that if i use predict(rddata) after read() it will get the value because read() returns the output of type uvm_reg_data_t. But i observed that at the same time o read operation the comparison of DUT and mirrored value happened.

May i know in which cases the DUT and mirrored value is compared.

I am not using compare() method and also auto_predict is disabled. But any idea which enables this comparison at the same time when read happens?

In reply to murali405:

To enable checking do : mirror(Status, UVM_CHECK). The default is UVM_NO_CHECK

In reply to murali405:

If “uvm_reg_data_logic_t” Returns ‘x’ here might be something wrong with the connection. This is only to debug your problem in some more detail.

In reply to chr_sue:

It is resolved . The mirrored value is getting updated using predict() method. In my environment the comparison happens whenever read from that register happens.
So i updated the mirrored value before calling Read() method and it worked.

In reply to murali405:

Can you tell me u on auto_predict method or u manually updated using predict method.

hi all,
I am getting both mirrored and desired values. But both are not getting at the same time(mirrored values are getting after some time) and am unable to figure it out. Can some one please help me in this issue.
Thanks in advance.

In reply to naveen-y:

hi all,
I am getting both mirrored and desired values. But both are not getting at the same time(mirrored values are getting after some time) and am unable to figure it out. Can some one please help me in this issue.
Thanks in advance.

Please tell me, how did you update mirrored and desired values? With less information you provided, I guess that the mirrored value is updated via bus monitor (explicited predict), then it will take a longer delay comparing to desired value.

In reply to cuonghl:

Thank you for replying. I have connected monitor(with analysis port) to the predictor(bus-in, implementation port in predictor) and I have done the set_auto_predict(1), in the ‘env’, which updates the mirrored_values automatically. And I have not used any explicit ‘predict’ method anywhere.
And one more doubt I have is that, I am getting the desired and mirrored values of different registers at different times. For example, if am getting the
desired value of ‘ctrl’ reg at time t, i get
mirrored value of ‘ctrl’ reg at time t+20 and
desired value of ‘div’ reg at time t+20, i get
mirrored value of ‘div’ reg at time t+40 and so on for the other registers(in the order in which I have written in sequence by using ‘write’ and ‘read’ register access methods).
Is it correct if we get the values of all the registers at different times?
And is it correct if we get the desired and mirrored values at different times?
Is it compulsory that we should get all the values at the same time?