Enumeration error in systemverilog

OVM
1

hi all:)
i declared an enumeration type like

typedef enum {RANDOM_CLOCK, FIXED_CLOCK} clocktype;

that i use in a module that generates a clock signal as shown below:

"RANDOMCLOCK":begin 
                     gen_CLK_period();
                     gen_CLK_high();
                     forever
                     begin
                       I.CLKRESET.CLK <= 1;
                       #(clockgen.high);
                       I.CLKRESET.CLK <= 0;
                       #(clockgen.period-clockgen.high);
                     end
                    end
                    
      "SETCLOCK":begin
                  set_CLK(I.clock_period, I.clock_high);
                  forever
                  begin
                    I.CLKRESET.CLK <= 1;
                    #(clockgen.high);
                    I.CLKRESET.CLK <= 0;
                    #(clockgen.period-clockgen.high);
                  end
                 end

when i compile i got:

Enum literal name 'RANDOM_CLOCK' already exists.
          Enum literal name 'FIXED_CLOCK' already exists.
          Typedef 'clocktype' multiply defined.

i do not know what do to. thanks in advance

2

You need to investigate

Typedef ‘clocktype’ multiply defined.
You probably included the definition twice. You should be using packages.

3

no, i don’t included twice the enumeration
i took advice and i put the enumeration in a package, but now i got a warning

'enums' already exists and will be overwritten.

i declared a package named ‘enums’ and i put the above enumeration in it

4

no, i don’t included twice the enumeration
i took advice and i put the enumeration in a package, but now i got a warning

'enums' already exists and will be overwritten.

i declared a package named ‘enums’ and i put the above enumeration in it

It looks to me like your compile filelist issue. My guess - you are passing the same file twice to the compiler - one perhaps via `include and another via command line/-f option etc.

Either show us more/full code or explore your compile script/command.

Srini
www.cvcblr.com/blog

5

thanks for answering sri.cvcblr; i include only once the package, i have not insert any command line;

below is my code regarding this topic that contains 2 files:

enums.sv

//package enums;
  
//the available types for generation of clock signal
typedef enum {RANDOM_CLOCK, FIXED_CLOCK} clocktype;

//endpackage

and clkgenblock.sv

`include "dutports.sv"
`include "gencomm.sv"
`include "intf.sv"
`include "enums.sv"

module clkgenblock(intf.CLKRESET I);
  
  CLOCKGEN clockgen;
  RESETGEN resetgen;
  
  initial begin
  clockgen = new();
  resetgen = new();
  end

  initial 
  begin
    I.CLKRESET.CLK = 0;
    case(I.ct)
      
      "RANDOM_CLOCK":begin 
                     gen_CLK_period();
                     gen_CLK_high();
                     forever
                     begin
                       I.CLKRESET.CLK <= 1;
                       #(clockgen.high);
                       I.CLKRESET.CLK <= 0;
                       #(clockgen.period-clockgen.high);
                     end
                    end
                    
      "FIXED_CLOCK":begin
                  set_CLK(I.clock_period, I.clock_high);
                  forever
                  begin
                    I.CLKRESET.CLK <= 1;
                    #(clockgen.high);
                    I.CLKRESET.CLK <= 0;
                    #(clockgen.period-clockgen.high);
                  end
                 end
    endcase
  end
endmodule

i use modelsim SE 6.5

when i compile i got:

** Error: enums.sv(4): Enum literal name 'RANDOM_CLOCK' already exists.
** Error: enums.sv(4): Enum literal name 'FIXED_CLOCK' already exists.
** Error: enums.sv(4): Typedef 'clocktype' multiply defined.
6

Show us your intf.sv file - what is data type of “ct”? Is that this “enum type”, if yes, how does that compile? Is it string by any chance? I’m surprised by your case choices being enclosed in “” (double quotes)

Srini
www.cvcblr.com/blog

7

intf.sv

`include "enums.sv"
`include "defines.sv"

interface intf();
  
  logic RESET; //RESET signal
  logic CLK; //CLK signal
  logic[1:0] ADDR; //the adress bus
  logic[7:0] DATA_IN; //the input data bus
  logic RD; //RD signal
  logic WR; //WR signal
  logic PWM_IN; //PWM_IN signal
  
  clocktype ct;
  int unsigned clock_period;
  int unsigned clock_high;
  
  //the interface signals that enter in the DUT
  modport DATAPATH(
                    input RESET,
                    input CLK,   
                    input ADDR,
                    input DATA_IN,
                    input RD,
                    input WR
                  );
  
  //the interface signals generated by the clkgenblock module
  modport CLKRESET(
                   output RESET,
                   output CLK
                  );
                  
  //the interface signal that is generated by pwm_in_block module    
  modport PWMPATH(
                   input PWM_IN
                 );
  
  modport PWMGEN( 
                  output PWM_IN
                ); 
                                
endinterface: intf
8

OK, my guess was right :-)

[QUOTE=kaes]intf.sv

`include "enums.sv"

The first enums.sv

So the tool complained during the other enums.sv at your top level. I suggest you do:

`include "dutports.sv"
`include "gencomm.sv"
`include "enums.sv"
`include "intf.sv"

module clkgenblock(intf.CLKRESET I);

And remove the enums.sv from intf.sv file. You will still have the “” issue I mentioned earlier.

I would classify this as error-message enhancement to your vendor - it could have shown the first inclusion of enums.sv to avoid these many typings :-)

This is one of the common issues with SV first tomers - it requires some thought on file inclusion/file list - unlike plain Verilog.

Regards
Srini
www.cvcblr.com/blog

9

thank you very much, but now i have another problem
in intf.sv when i compile i got: ‘clocktype’ is an unknown type.
it seems that 'include enums.sv above 'include intf.sv does not have effect

10

It is always good to use ifdef, ifndef directives so that it automatically avoids the double declaration.

ifndef _ENUMS_SV_ define ENUMS_SV
…
…
…
`endif

So whenever next include “enums.sv” will come it will first check “ENUMS_SV” is defined or not if defined it will not compile till associated “`endif”.

Regards,