Mehod/function overloading

SystemVerilog
1

We have method overriding in system verilog, where the method in derived class can override the base class’s method. Both the methods should be of same name and same signature.

Do we have method overloading in system verilog? I mean does SV supports this concept?

If it is supported, can any body tell me the context in testbench or test development?

Thanks
Rajeshwar

2

Yes, this is a very basic principal of a class based testbench. Search the internet for “SystemVerilog virtual method” for some examples.

3

AFAIK “overloading” is not available in SV (unlike in VHDL for instance). Maybe if you explain what you need, we can help you find a way to do it in SV.

Ajeetha, CVC

4

In reply to ajeetha:

Overriding/overloading a method with the same signature can be the same as defining a virtual method. The term method overloading usually applies to methods with a different signature (i.e. different types or numbers of arguments).

5

I agree with Dave. Function overloading normally refers to the case where you have the same function name with different signatures.

A simple example in C++;

class C {
virtual void print(int x);
virtual void print(float y);
}

Note the same function “print” has two different signatures. This is a very useful feature. However this is not supported in
SystemVerilog as far as I know. Not sure if there are plans in the committee to support this in the future.

Thanks

Logie.

6

In reply to logie:

Thank you all.

@Dave, I understand the method/function overriding in System verilog. I was looking for the scenario like Logie explained, where we have the two methods with same name but different signatures in SystemVerilog. So it is not supported for sure in systemverilog.

Thanks,
Rajeshwar

7

In reply to RAJESHWAR:

OK. You originally wrote

Both the methods should be of same name and same signature.

AFAIK, there are no plans to add this to SystemVerilog.

8

In reply to dave_59:

Thanks Dave.

“We have method overriding in system verilog, where the method in derived class can override the base class’s method. Both the methods should be of same name and same signature”

Quote:
Both the methods should be of same name and same signature.

Actually, I mentioned the above thing continuing the context of method overriding.

Any way, I am sorry for the confusion created.

Thank you.

Rajeshwar

9

In reply to RAJESHWAR:

Static methods can be overloaded, that means a class can have more than one static method of same name. But static methods cannot be overridden, even if you declare a same static method in derived class it has nothing to do with the same method of base class…Source

Dov

10

In reply to ephraimdov:

Dov,

This is not true in SystemVerilog - there is no method overloading .

Dave

11

In reply to ephraimdov:

Even static method does not support overloading.