SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
20

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for suggestion .

Could anyone tell, what is the syntax error here ? I am getting the compilation error.

property out_bits_incr_prpty;
  bit[7:0] v;
//  @(posedge monclk_output) disable iff(!i_en_fll)
@(posedge sampled_monclk) disable iff (!i_en_fll)
  ##1  1   |->   if (monclk_count < i_count)
   v=incr(o_prog_out_fll, sar_mask ,monclk_count, i_count) ##0 v 
  else
   v=decr(o_prog_out_fll, sar_mask ,monclk_count, i_count)  ##0 v ;
endproperty