SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
18

In reply to rkg_:
I don’t see anything wrong, but I am seen what you want me to see; maybe there are other places where you call the function. If the antecedent fails, the consequent is not triggered. The true action block may be triggered though because a vacuously true condition is true.


module m; 
  bit a=0, clk; 
  
  initial forever #10 clk = !clk;
  ap: assert property(@(posedge clk) a |-> 1) $display("%t Test vacuous true a=", $realtime, $sampled(a));  
   
  initial begin
    repeat (6) begin   
      @(posedge clk);
      $display("%t a= ", $realtime, a);
      a<= !a;     
    end ;     
    $finish;
  end
endmodule
//--------
# KERNEL:                   10 a= 0
# KERNEL:                   10 Test vacuous true a=0
# KERNEL:                   30 a= 1
# KERNEL:                   30 Test vacuous true a=1
# KERNEL:                   50 a= 0
...

Things you can do:

  • Use the debugging tool of the simulator. Some tools have a thread viewer that traces what is going on.
  • Write a simple model with a function call and see how your simulator handles that.
  • Check your action block

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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