SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
15

In reply to rkg_:

And below is the algorithm for property but not sure how to implement this .
Algorithm :

  1. calculate the index of fll_out_bits where 1’b1 is present (eg. if fll_out_bits 10100000 (big endian )then index should be 5 in this case)
  2. for incr : (index-1 = 5-1 = 4) so position 4 should be 1 and rest other position value should be same like previous ( e.g 10110000)
  3. for decr : if input is 10100000 (index -1 = 5-1 = 4) so position 4 should be 1 and (index) position 5 will be 0 and rest should be same e.g(10010000)

I hope , I am able to explain the algorithm.

if above code (i have mixed incr and decr) looks good then i don’t need to write code for above algorithm but if not work i have to implement this .

Could you please help