SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
14

In reply to ben@SystemVerilog.us:

Hi Ben

Here my intention is sar_mask should retain the value at every every function call . will it work ?

fll_out_bits changes at every negedge sampled_monclk and my function should get called at every negedge sampled_monclk and same time assertion should get trigger


function bit incr_decr (logic [7:0]fll_out_bits , logic [7:0]mon_clk_count, logic [7:0]counts);
 bit[7:0] sar_mask = 8'b10000000;
//INCR
begin
if (mon_clk_count < counts)
begin 
  fll_out_bits = fll_out_bits | (sar_mask >>1);
 sar_mask = sar_mask >> 1'b1;
end
//DECR
else if (mon_clk_counts >= counts)
begin
 fll_out_bits = (fll_out_bits & !(sar_mask)) | (sar_mask >> 1)
 sar_mask = sar_mask >> 1'b1;
end
return fll_out_bits ;
end
endfunction 


property out_bits_decr_prpty;
  bit v;
  @(negedge  sampled_monclk) disable iff(!en_fll)
  
  1'b1 |=> (1, v=incr_decr(fll_out_bits ,monclk_count, i_count)) ##0 v;
endproperty

Error :
Unexpected identifier ‘sar_mask’ after completed expression