SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
13

In reply to rkg_:

I may have misunderstood your requirements, but the shift left/right was what I interpreted from your posts.
You need to clearly define the requirements and implement the code accordingly.
You have the right concepts.
If the increment /decrement is ccmplex use a function call from the sequence_match_item e. G,

 
function bit dec(logic[your _range]:
  ... // your decrement algorithm 
 return value; //
endfunction 

property out_bits_decr_prpty;
  @(negedge refclk_output) disable iff(!en_reset)
  bit v;
  (negclk_count > count) && Enable|=> 
       (1, v=dec(out_bits)) ##0 v;
       //mout_bits == {$past(out_bits[2:0]), 1'b0)};  //before
       //out_bits == {$past(1'b0,out_bits[3:1])};   // modified 
  // was: (out_bits < ($past(out_bits, 1));
endproperty