SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
8

In reply to rkg_:

Hi Ben,

i can see decr_property get trigger when monclk_cout < i_count and same incr_property get trigger when monclk_count >= i_count

Code :

property prog_out_fll_incr_prpty;
		@(negedge  refclk_sig_d1) disable iff(!i_en_fll)
		(monclk_count < i_count) |=> (o_prog_out_fll == {1'b1,$past(o_prog_out_fll[7:1])} );
	endproperty


property prog_out_fll_decr_prpty;
		@(negedge  refclk_sig_d1) disable iff(!i_en_fll)
                                              
		(monclk_count >= i_count) |=> (o_prog_out_fll == {1'b0,$past(o_prog_out_fll[7:1])}) ;
	endproperty

Waveform :

Am i doing any mistake ?