SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
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11

In reply to rkg_:

I don’t know if those solid values are Xs for monclk_count at sampling times, but if Xs it should not trigger.
For things like that, you can add debugging signals. For example


  event e_p, e_m;
always @(negedge  refclk_sig_d1)  begin 
	if(monclk_count < i_count)  -> e_m; 
 	if(monclk_count >= i_count) -> e_p;

Offhand, things look OK, I seriously doubt that the vendor is making such a silly mistake.