SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
4

In reply to rkg_:
Your requirements are ambiguous, do you want an increment/decrement by 1 or
do you want a shift left/right. Also what about the rollover?
bit[3:0] a=4’b1111;
a + 1’b1 == 4’b0000;


// ** if (mon_count < count) and Enable = 1 then OUT_BITS should increment like 11000000 (i.e 198) 
// again sample at mon_clk if (mon_count < count) OUT_BITS should 11100000 (i.e 224) like it can reach upto 8'b11111111
//  but if (mon_count > count ) it should do the decrement like (OUT_BITS is 10000000 
// then OUT_BITS should decrement to 01000000) . it will so on.
property out_bits_incr_prpty;
  @(negedge refclk_output) disable iff(!reset)
  (monclk_count <  count) && Enable|=> out_bits == $past(out_bits) + 1'b1;
   // was: (out_bits > ($past(out_bits, 1) );
endproperty 
/* check the out bits decrement */
property out_bits_decr_prpty;
  @(negedge refclk_output) disable iff(!en_reset)
  (negclk_count > count) && Enable|=> out_bits == $past(out_bits) - 1'b1; 
  // was: (out_bits < ($past(out_bits, 1));
endproperty