SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for suggestion.

Is it correct way ?

property out_bits_incr_prpty;
		@(negedge refclk_output) disable iff(!reset)
		(monclk_count <  count) |=> (out_bits > ($past(out_bits, 1) );
	endproperty
/* check the out bits decrement */
property out_bits_decr_prpty;
		@(negedge refclk_output) disable iff(!en_reset)
		(negclk_count > count) |=> (out_bits < ($past(out_bits, 1));
	endproperty

please correct me if i am wrong