SVA- How we can write property such that it will check OUT_BITS increment and decrement

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

HI,

I don’t want incr/decr by 1.

its should be like if (mon_count < count ) out_bits should get increment like from 10000000 to 11000000 like so on and if mon_count > count out_bits should be decrement like from 10000000 to 01000000 and so on

And It should not rollover means out_bits will not toggles once it reach to 11111111 or 00000000.