Verification Academy

Topic	Replies	Views	Activity
A queue I created never pop front SystemVerilog SystemVerilog	3	588	July 12, 2022
What is an API? UVM UVM	2	3519	July 12, 2022
Questions SystemVerilog SystemVerilog	1	463	July 11, 2022
Working of ' matches ' Operator SystemVerilog SystemVerilog , Working-of--matches--Operator	2	921	July 11, 2022
Uvm_mem UVM UVM , uvm_mem , uvm_mem_mam	0	450	July 11, 2022
Error Msg. Could not find member 'seq_item_export' UVM UVM , seq_item_export	2	654	July 9, 2022
N*n matrix SystemVerilog SystemVerilog	8	1048	July 9, 2022
System verilog "this" keyword SystemVerilog SystemVerilog , System-Verilog	1	760	July 8, 2022
Associative Array System Verilog SystemVerilog SystemVerilog	1	436	July 7, 2022
Set Membership Operator SystemVerilog SystemVerilog , SET-Membership-Operator	2	933	July 7, 2022
How to write wildcardbins using range? SystemVerilog SystemVerilog , wildcard	2	2237	July 7, 2022
Analysis port wrapped in a callback UVM UVM	1	586	July 7, 2022
SVA for 150MHz clock frequency with +5% or -5% margin SystemVerilog SystemVerilog , system-verilog-assertions	1	606	July 7, 2022
Setting uvm agent active or passive UVM UVM	1	615	July 6, 2022
System verilog assertion question SystemVerilog SystemVerilog	7	1455	July 6, 2022
Bin should be hit based on how frequent it is occured Coverage Coverage	1	365	July 6, 2022
Why pre_shutdown phase occurs at 0ns? UVM SystemVerilog , UVM , UVM_PHASE , run_phase , shutdown_phase	1	679	July 6, 2022
Constraint random variable SystemVerilog SystemVerilog , rand-and-randc , byte-signed-within-range	4	704	July 6, 2022
What is the best way to fast check the miss matched register value between dut and ral? UVM UVM , RAL-UVM-REGISTER	0	342	July 6, 2022
Conditional instantiation of components UVM UVM , activepassive-agent-configuration , uvm-config_db , conditional-compilation	0	400	July 5, 2022
Are soft constraints good or bad? UVM UVM , soft-constranit	1	539	July 5, 2022
Error: (vsim-PLI-3537) $dumpvars() : Argument 2 is invalid SystemVerilog SystemVerilog , dumpvars-error	1	665	July 5, 2022
NO_VIF: virtual interface must be set for:test.env.vif UVM UVM , Systemverilog-UVM-RAL	1	1009	July 5, 2022
Example of passing a static array of bytes from SystemVerilog to C via DPI SystemVerilog SystemVerilog , System-Verilog , Systemverilog-DPI	6	1496	July 5, 2022
Dist problem SystemVerilog SystemVerilog	2	468	July 4, 2022
Usage of 4 state & 2 state data type SystemVerilog SystemVerilog , data-type-recommendation-for-usage	1	1389	July 4, 2022
Question about bind SystemVerilog SystemVerilog	1	811	July 4, 2022
Why am i not able to increase the size of dynamic array SystemVerilog SystemVerilog , dynamic-array-memory-allocation	1	568	July 4, 2022
What is meant by Verification Plan? SystemVerilog SystemVerilog	1	354	July 4, 2022
RAL model byte_en UVM UVM , RAL-UVM	2	973	July 4, 2022