Error: (vsim-PLI-3537) $dumpvars() : Argument 2 is invalid

SystemVerilog
,
1

Hi,

For a project a have the top module (top1.sv) and I want to generate the waveform of a test (Test1.sv). The code for this is:

ifdef DUMP_VCD $dumpfile("test1.vcd"); $dumpvars(0, test1.main_intf[0]); $dumpon; endif

Where main_intf is an instance of a interface of 64 lanes in test1.sv

module test1;
main_intf1 main_intf64;

But when I try to get the waveform I get the error:

** Error: (vsim-PLI-3537) $dumpvars() : Argument 2 is invalid. : /home/jose/tests/test1.sv(44)

2

In reply to Jose1980:

Technically, the LRM says the 2nd argument to $dumpvars is a list_of_modules_or_variables, which would exclude interface instances. I’m guessing that was an oversight in the SystemVerilog LRM leftover from Verilog.

I would contact your tool vendor about it.