Question about bind

SystemVerilog
1

Hi All,
there are two module ( dut and test) in same hierarchy.
I know there are two ways to connect them.
bind: dut test test_inst(.) or test test_inst(.)
My question is ,if DUT and TEST are in same hierarchy or level, it seems that there are no special advantage using bind method.
Am i correct?

2

In reply to peter:
Binding assertions to scopes or instances
To keep verification code separate from the design code
SystemVerilog provides a bind construct that is used to specify one or more instantiations of a module, interface, program, or checker without modifying the code of the target.
This also keeps the synthesis of the RTL separate from the assertion code that may also add support logic. Synthesis tools ignore the binded module/checker.

So, for example, instrumentation code or assertions that are encapsulated in a module, interface, program, or checker can be instantiated in a target module or a module instance in a non-intrusive manner. Similarly, instrumentation code that is encapsulated in an interface can be bound to a target interface or interface instance.

Bottom line, use the bind appropriately. Typically, the bind is used to link an entity that will not be synthesized, like an SVA checker or module into the DUT.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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