SVA for 150MHz clock frequency with +5% or -5% margin

SystemVerilog
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1

Hi All,
i want to verify clock frequency of 150Mhz with a margin of +5% or -5% using system verilog assertions.

for ex - in my simulation even if i am getting 148mhz clock frequency my assertions should pass. is there any way to do it.

Regards,
Ravi

2

In reply to ravishekhar0004:

See How to write assertions for clock frequencies | Verification Academy
checking clock period using system verilog assertion | Verification Academy
put the range in the comparison, e.g., a >=min && a <= max