Set Membership Operator

SystemVerilog
,
1

Hi,
What happens when a set membership operator is used without any range?
For example in this case: addr inside {RAM_START_ADDR};
Does this mean “addr” can take up any value from 0 to RAM_START_ADDR?

2

No, “addr” does not match any value from 0 to RAM_START_ADDR; it only matches the value equal to RAM_START_ADDR, as this self-contained testbench shows:

module tb;

localparam RAM_START_ADDR = 4;

initial begin
    for (int addr=0; addr<8; addr++) begin
        if (addr inside {RAM_START_ADDR}) begin
            $display("addr=%0d inside", addr);
        end else begin
            $display("addr=%0d outside", addr);
        end
    end
end

endmodule

When you run the simulation, you get this output:

addr=0 outside
addr=1 outside
addr=2 outside
addr=3 outside
addr=4 inside
addr=5 outside
addr=6 outside
addr=7 outside

Only the value matching RAM_START_ADDR is considered “inside” the range.

3

In reply to gsulliva:

Only the value matching RAM_START_ADDR is considered “inside” the range.

Another way to think of it is you only provided one value for the set; RAM_START_ADDR. addr either inside the set, or not.