Constraint random variable

SystemVerilog
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1

Hi,

How to constraint a random variable defined as rand byte unsigned?

For example, if I want to control the random variable by assigning 0x1 value,

rand byte unsigned      data[];
data= 32'h1

Is this the correct way to define it?

2

In reply to basilleaf:

rand byte unsigned  data;
constraint c1 {data == 32'h1;}
3

In reply to Shashank Gurijala:

Hi,

  1. May i know why its define as 32’h1 and not 4’h1?
  2. Since its a data array, it shouldnt be define as data = '{32’h1}?
4

In reply to basilleaf:

Your question is not very clear.What does a 0x1 value mean for an array? do you mean each element of tha array to have the value 8’h1? How big is the array?

5

In reply to dave_59:

I want to write specific address with specific value by constraining the seq_item. But Im not sure how to constrain the random variable, data_bytes to have specific value (0x1) since its in bytes unsigned and the source is bit[31:0].

rand longint unsigned            address;               
 rand bit [31:0]                  len;                   //Size of the total bytes to be writen or read
 rand byte  unsigned              data_bytes[];          //size of the array shall match the value specified sing ~len~.

`uvm_create_on(seq_item, pick_sqcr("mst_sqr_0"))
           seq_item.address = 32'h0100_1220;
           seq_item.data_bytes = 32'h1;
           start_item(seq_item);
	    `uvm_info(get_type_name(), $sformatf("Printing seq item"), UVM_NONE); 
              seq_item.sprint();
            finish_item(seq_item);